[PATCH] D21061: [ARM] Remove exit-on-error flag from test (PR27765)

[Diana Picus via llvm-commits]

rovka updated this revision to Diff 60352.
rovka added a comment.

Added a test for PowerPC.

X86 proved a bit tricky, because there is some special code in X86TargetLowering::getRegForInlineAsmConstraint in case the generic getRegForInlineAsmConstraint didn't return what X86 wanted. It even has this comment:
// Handle references to XMM physical registers that got mapped into the
// wrong class.  This can happen with constraints like {xmm0} where the
// target independent register mapper will just pick the first match it can
// find, ignoring the required type.

So I'm guessing X86 is trying pretty hard to avoid this code path, so even if I managed to make it go through there it would probably be a bug.

PowerPC on the other hand seems to be handling things more similarly to ARM, and it can also cope with the bitcast that this patch is adding.


http://reviews.llvm.org/D21061

Files:
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll
  test/CodeGen/PowerPC/inline-asm-scalar-to-vector-error.ll

Index: test/CodeGen/PowerPC/inline-asm-scalar-to-vector-error.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/inline-asm-scalar-to-vector-error.ll
@@ -0,0 +1,14 @@
+; RUN: not llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8a -mattr=+altivec %s -o - 2>&1 | FileCheck %s
+
+define hidden void @f(i32 %x) {
+  ; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type
+  tail call void asm sideeffect "nop", "{v1}"(i32 %x) nounwind
+
+  ; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type
+  tail call void asm sideeffect "nop", "{vsl1}"(i32 %x) nounwind
+
+  ; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type
+  tail call void asm sideeffect "nop", "{vsh1}"(i32 %x) nounwind
+
+  ret void
+}
Index: test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll
===================================================================
--- test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll
+++ test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll
@@ -1,10 +1,11 @@
-; RUN: not llc -mtriple=arm-eabi -mcpu=cortex-a8 -exit-on-error %s -o - 2>&1 | FileCheck %s
+; RUN: not llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - 2>&1 | FileCheck %s
 
 ; Check for error message:
 ; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type
+; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type
 
 define hidden void @f(i32* %corr, i32 %order) nounwind ssp {
-  tail call void asm sideeffect "vst1.s32 { ${1:q}, ${2:q} }, [$0]", "r,{q0},{q1}"(i32* %corr, <2 x i64>* undef, <2 x i64>* undef) nounwind, !srcloc !0
+  tail call void asm sideeffect "vst1.s32 { ${1:q}, ${2:q} }, [$0]", "r,{q0},{q1}"(i32* %corr, <2 x i64>* undef, i32 %order) nounwind, !srcloc !0
   ret void
 }
 
Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -446,9 +446,11 @@
          "Failed to tile the value with PartVT!");
 
   if (NumParts == 1) {
-    if (PartEVT != ValueVT)
+    if (PartEVT != ValueVT) {
       diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
                                         "scalar-to-vector conversion failed");
+      Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
+    }
 
     Parts[0] = Val;
     return;


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