[llvm] r272256 - [mips][microMIPS] Add CodeGen support for SEL.*, SELEQZ, SELNEZ, SELEQZ.*, SELNEZ.* and CMP.condn.fmt instructions
Zlatko Buljan via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 9 04:15:54 PDT 2016
Author: zbuljan
Date: Thu Jun 9 06:15:53 2016
New Revision: 272256
URL: http://llvm.org/viewvc/llvm-project?rev=272256&view=rev
Log:
[mips][microMIPS] Add CodeGen support for SEL.*, SELEQZ, SELNEZ, SELEQZ.*, SELNEZ.* and CMP.condn.fmt instructions
Differential Revision: http://reviews.llvm.org/D20862
Modified:
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
llvm/trunk/test/CodeGen/Mips/fcmp.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/select-int.ll
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=272256&r1=272255&r2=272256&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Thu Jun 9 06:15:53 2016
@@ -186,8 +186,8 @@ class SEL_S_MMR6_ENC : POOL32F_SEL_FM_MM
class SEL_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.d", 1, 0b010111000>;
class SELEQZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.s", 0, 0b000111000>;
class SELEQZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.d", 1, 0b000111000>;
-class SELENZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selenz.s", 0, 0b001111000>;
-class SELENZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selenz.d", 1, 0b001111000>;
+class SELNEZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.s", 0, 0b001111000>;
+class SELNEZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.d", 1, 0b001111000>;
class CLASS_S_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.s", 0, 0b001100000>;
class CLASS_D_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.d", 1, 0b001100000>;
@@ -838,69 +838,69 @@ class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_
multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
RegisterOperand FGROpnd> {
- def CMP_AF_#NAME : POOL32F_CMP_FM<
+ def CMP_AF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
- CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
- def CMP_UN_#NAME : POOL32F_CMP_FM<
+ def CMP_UN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
- CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>, HARDFLOAT,
ISA_MICROMIPS32R6;
- def CMP_EQ_#NAME : POOL32F_CMP_FM<
+ def CMP_EQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
- CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>, HARDFLOAT,
ISA_MICROMIPS32R6;
- def CMP_UEQ_#NAME : POOL32F_CMP_FM<
+ def CMP_UEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
- CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>, HARDFLOAT,
ISA_MICROMIPS32R6;
- def CMP_LT_#NAME : POOL32F_CMP_FM<
+ def CMP_LT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
- CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>, HARDFLOAT,
ISA_MICROMIPS32R6;
- def CMP_ULT_#NAME : POOL32F_CMP_FM<
+ def CMP_ULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
- CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>, HARDFLOAT,
ISA_MICROMIPS32R6;
- def CMP_LE_#NAME : POOL32F_CMP_FM<
+ def CMP_LE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
- CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>, HARDFLOAT,
ISA_MICROMIPS32R6;
- def CMP_ULE_#NAME : POOL32F_CMP_FM<
+ def CMP_ULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
- CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>, HARDFLOAT,
ISA_MICROMIPS32R6;
- def CMP_SAF_#NAME : POOL32F_CMP_FM<
+ def CMP_SAF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
- CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
- def CMP_SUN_#NAME : POOL32F_CMP_FM<
+ def CMP_SUN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
- CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
- def CMP_SEQ_#NAME : POOL32F_CMP_FM<
+ def CMP_SEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
- CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
- def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
+ def CMP_SUEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
- CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
- def CMP_SLT_#NAME : POOL32F_CMP_FM<
+ def CMP_SLT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
- CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
- def CMP_SULT_#NAME : POOL32F_CMP_FM<
+ def CMP_SULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
- CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
- def CMP_SLE_#NAME : POOL32F_CMP_FM<
+ def CMP_SLE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
- CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
- def CMP_SULE_#NAME : POOL32F_CMP_FM<
+ def CMP_SULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
- CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
}
@@ -974,8 +974,8 @@ class SEL_D_MMR6_DESC : COP1_SEL_DESC_BA
class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
-class SELENZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
-class SELENZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
+class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
+class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
class CLASS_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
@@ -1478,15 +1478,15 @@ def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W
ISA_MICROMIPS32R6;
def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC,
ISA_MICROMIPS32R6;
-def SEL_S_MMR6 : StdMMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;
-def SEL_D_MMR6 : StdMMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6;
-def SELEQZ_S_MMR6 : StdMMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,
+def SEL_S_MMR6 : R6MMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;
+def SEL_D_MMR6 : R6MMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6;
+def SELEQZ_S_MMR6 : R6MMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,
ISA_MICROMIPS32R6;
-def SELEQZ_D_MMR6 : StdMMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,
+def SELEQZ_D_MMR6 : R6MMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,
ISA_MICROMIPS32R6;
-def SELENZ_S_MMR6 : StdMMR6Rel, SELENZ_S_MMR6_ENC, SELENZ_S_MMR6_DESC,
+def SELNEZ_S_MMR6 : R6MMR6Rel, SELNEZ_S_MMR6_ENC, SELNEZ_S_MMR6_DESC,
ISA_MICROMIPS32R6;
-def SELENZ_D_MMR6 : StdMMR6Rel, SELENZ_D_MMR6_ENC, SELENZ_D_MMR6_DESC,
+def SELNEZ_D_MMR6 : R6MMR6Rel, SELNEZ_D_MMR6_ENC, SELNEZ_D_MMR6_DESC,
ISA_MICROMIPS32R6;
def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC,
ISA_MICROMIPS32R6;
@@ -1568,3 +1568,20 @@ def : MipsPat<(store GPRMM16:$src, addri
(SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;
def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
(SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6;
+
+def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
+ (OR_MM (SELNEZ_MMR6 i32:$t, i32:$cond),
+ (SELEQZ_MMR6 i32:$f, i32:$cond))>,
+ ISA_MICROMIPS32R6;
+def : MipsPat<(select i32:$cond, i32:$t, immz),
+ (SELNEZ_MMR6 i32:$t, i32:$cond)>,
+ ISA_MICROMIPS32R6;
+def : MipsPat<(select i32:$cond, immz, i32:$f),
+ (SELEQZ_MMR6 i32:$f, i32:$cond)>,
+ ISA_MICROMIPS32R6;
+
+defm : SelectInt_Pats<i32, OR_MM, XORI_MMR6, SLTi_MM, SLTiu_MM, SELEQZ_MMR6,
+ SELNEZ_MMR6, immZExt16, i32>, ISA_MICROMIPS32R6;
+
+defm S_MMR6 : Cmp_Pats<f32, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
+defm D_MMR6 : Cmp_Pats<f64, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=272256&r1=272255&r2=272256&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td Thu Jun 9 06:15:53 2016
@@ -188,53 +188,80 @@ class CMP_CONDN_DESC_BASE<string CondStr
multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
RegisterOperand FGROpnd>{
let AdditionalPredicates = [NotInMicroMips] in {
- def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>,
+ def CMP_F_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>,
CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>,
+ MipsR6Arch<!strconcat("cmp.af.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
+ def CMP_UN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,
+ MipsR6Arch<!strconcat("cmp.un.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
+ def CMP_EQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>,
+ MipsR6Arch<!strconcat("cmp.eq.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
+ def CMP_UEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
+ FIELD_CMP_COND_UEQ>,
CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>,
+ MipsR6Arch<!strconcat("cmp.ueq.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
+ def CMP_LT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>,
+ MipsR6Arch<!strconcat("cmp.lt.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
+ def CMP_ULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
+ FIELD_CMP_COND_ULT>,
CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>,
+ MipsR6Arch<!strconcat("cmp.ult.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
+ def CMP_LE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>,
+ MipsR6Arch<!strconcat("cmp.le.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
+ def CMP_ULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
+ FIELD_CMP_COND_ULE>,
CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>,
+ MipsR6Arch<!strconcat("cmp.ule.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_SAF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SAF>,
+ def CMP_SAF_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
+ FIELD_CMP_COND_SAF>,
CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>,
+ MipsR6Arch<!strconcat("cmp.saf.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_SUN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUN>,
+ def CMP_SUN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
+ FIELD_CMP_COND_SUN>,
CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>,
+ MipsR6Arch<!strconcat("cmp.sun.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
+ def CMP_SEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
+ FIELD_CMP_COND_SEQ>,
CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
+ MipsR6Arch<!strconcat("cmp.seq.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_SUEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUEQ>,
+ def CMP_SUEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
+ FIELD_CMP_COND_SUEQ>,
CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>,
+ MipsR6Arch<!strconcat("cmp.sueq.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_SLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLT>,
+ def CMP_SLT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
+ FIELD_CMP_COND_SLT>,
CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>,
+ MipsR6Arch<!strconcat("cmp.slt.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_SULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULT>,
+ def CMP_SULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
+ FIELD_CMP_COND_SULT>,
CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>,
+ MipsR6Arch<!strconcat("cmp.sult.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_SLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLE>,
+ def CMP_SLE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
+ FIELD_CMP_COND_SLE>,
CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>,
+ MipsR6Arch<!strconcat("cmp.sle.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_SULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULE>,
+ def CMP_SULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
+ FIELD_CMP_COND_SULE>,
CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>,
+ MipsR6Arch<!strconcat("cmp.sule.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
}
}
@@ -523,11 +550,11 @@ class COP1_SEL_DESC_BASE<string instr_as
string Constraints = "$fd_in = $fd";
}
-class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
+class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd>, MipsR6Arch<"sel.d"> {
// We must insert a SUBREG_TO_REG around $fd_in
bit usesCustomInserter = 1;
}
-class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
+class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>, MipsR6Arch<"sel.s">;
class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
: MipsR6Arch<instr_asm> {
@@ -580,10 +607,14 @@ class SELEQNEZ_DESC_BASE<string instr_as
list<dag> Pattern = [];
}
-class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
-class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
-class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
-class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
+class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>,
+ MipsR6Arch<"seleqz.s">;
+class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>,
+ MipsR6Arch<"seleqz.d">;
+class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>,
+ MipsR6Arch<"selnez.s">;
+class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>,
+ MipsR6Arch<"selnez.d">;
class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
dag OutOperandList = (outs FGROpnd:$fd);
@@ -799,17 +830,19 @@ let AdditionalPredicates = [NotInMicroMi
def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
}
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
-def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
let AdditionalPredicates = [NotInMicroMips] in {
- def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, HARDFLOAT;
- def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6, HARDFLOAT;
-}
-def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
-let AdditionalPredicates = [NotInMicroMips] in {
- def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6, HARDFLOAT;
- def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6, HARDFLOAT;
- def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT;
- def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
+ def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
+ def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
+ def SELEQZ_D : R6MMR6Rel, SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6,
+ HARDFLOAT;
+ def SELEQZ_S : R6MMR6Rel, SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6,
+ HARDFLOAT;
+ def SELNEZ_D : R6MMR6Rel, SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6,
+ HARDFLOAT;
+ def SELNEZ_S : R6MMR6Rel, SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6,
+ HARDFLOAT;
+ def SEL_D : R6MMR6Rel, SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT;
+ def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
}
def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
@@ -855,8 +888,10 @@ def : MipsPat<(setne VT:$lhs, VT:$rhs),
(NOROp (!cast<Instruction>("CMP_EQ_"#NAME) VT:$lhs, VT:$rhs), ZEROReg)>;
}
-defm S : Cmp_Pats<f32, NOR, ZERO>, ISA_MIPS32R6;
-defm D : Cmp_Pats<f64, NOR, ZERO>, ISA_MIPS32R6;
+let AdditionalPredicates = [NotInMicroMips] in {
+ defm S : Cmp_Pats<f32, NOR, ZERO>, ISA_MIPS32R6;
+ defm D : Cmp_Pats<f64, NOR, ZERO>, ISA_MIPS32R6;
+}
// i32 selects
multiclass SelectInt_Pats<ValueType RC, Instruction OROp, Instruction XORiOp,
@@ -895,6 +930,7 @@ def : MipsPat<(select (Opg (setne RC:$co
(SELEQZOp RC:$f, RC:$cond)>;
}
+let AdditionalPredicates = [NotInMicroMips] in {
defm : SelectInt_Pats<i32, OR, XORi, SLTi, SLTiu, SELEQZ, SELNEZ,
immZExt16, i32>, ISA_MIPS32R6;
@@ -908,3 +944,4 @@ def : MipsPat<(select i32:$cond, i32:$t,
def : MipsPat<(select i32:$cond, immz, i32:$f),
(SELEQZ i32:$f, i32:$cond)>,
ISA_MIPS32R6;
+}
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=272256&r1=272255&r2=272256&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Jun 9 06:15:53 2016
@@ -1071,6 +1071,7 @@ MipsTargetLowering::EmitInstrWithCustomI
case Mips::DMODU_MM64R6:
return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true);
case Mips::SEL_D:
+ case Mips::SEL_D_MMR6:
return emitSEL_D(MI, BB);
case Mips::PseudoSELECT_I:
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=272256&r1=272255&r2=272256&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Thu Jun 9 06:15:53 2016
@@ -525,10 +525,12 @@ def BC1TL : MMRel, BC1F_FT<"bc1tl", brta
BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
/// Floating Point Compare
-def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,
- ISA_MIPS1_NOT_32R6_64R6;
-def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
- ISA_MIPS1_NOT_32R6_64R6, FGR_32;
+let AdditionalPredicates = [NotInMicroMips] in {
+ def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,
+ ISA_MIPS1_NOT_32R6_64R6;
+ def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
+ ISA_MIPS1_NOT_32R6_64R6, FGR_32;
+}
let DecoderNamespace = "Mips64" in
def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
ISA_MIPS1_NOT_32R6_64R6, FGR_64;
Modified: llvm/trunk/test/CodeGen/Mips/fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fcmp.ll?rev=272256&r1=272255&r2=272256&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fcmp.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/fcmp.ll Thu Jun 9 06:15:53 2016
@@ -12,10 +12,26 @@
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-CMP
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MM32R3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MMR6 \
+; RUN: -check-prefix=MM32R6
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MMR6 \
+; RUN: -check-prefix=MM64R6
define i32 @false_f32(float %a, float %b) nounwind {
; ALL-LABEL: false_f32:
-; ALL: addiu $2, $zero, 0
+; 32-C: addiu $2, $zero, 0
+
+; 32-CMP: addiu $2, $zero, 0
+
+; 64-C: addiu $2, $zero, 0
+
+; 64-CMP: addiu $2, $zero, 0
+
+; MM-DAG: lui $2, 0
%1 = fcmp false float %a, %b
%2 = zext i1 %1 to i32
@@ -41,6 +57,16 @@ define i32 @oeq_f32(float %a, float %b)
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.eq.s $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp oeq float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -65,6 +91,16 @@ define i32 @ogt_f32(float %a, float %b)
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ule.s $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
+; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ogt float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -89,6 +125,16 @@ define i32 @oge_f32(float %a, float %b)
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ult.s $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
+; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp oge float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -113,6 +159,16 @@ define i32 @olt_f32(float %a, float %b)
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.olt.s $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp olt float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -137,6 +193,16 @@ define i32 @ole_f32(float %a, float %b)
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ole.s $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ole float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -163,6 +229,17 @@ define i32 @one_f32(float %a, float %b)
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ueq.s $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: nor $[[T2:[0-9]+]], $[[T1]]
+; MMR6-DAG: andi16 $2, $[[T2]], 1
+
%1 = fcmp one float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -189,6 +266,17 @@ define i32 @ord_f32(float %a, float %b)
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.un.s $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG: andi16 $2, $[[T2]], 1
+
%1 = fcmp ord float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -213,6 +301,16 @@ define i32 @ueq_f32(float %a, float %b)
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ueq.s $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ueq float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -237,6 +335,16 @@ define i32 @ugt_f32(float %a, float %b)
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ole.s $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
+; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ugt float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -261,6 +369,16 @@ define i32 @uge_f32(float %a, float %b)
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.olt.s $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
+; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp uge float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -285,6 +403,15 @@ define i32 @ult_f32(float %a, float %b)
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ult.s $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp ult float %a, %b
%2 = zext i1 %1 to i32
@@ -310,6 +437,16 @@ define i32 @ule_f32(float %a, float %b)
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ule.s $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ule float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -336,6 +473,17 @@ define i32 @une_f32(float %a, float %b)
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.eq.s $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG: andi16 $2, $[[T2]], 1
+
%1 = fcmp une float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -360,6 +508,16 @@ define i32 @uno_f32(float %a, float %b)
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.un.s $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp uno float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -367,7 +525,15 @@ define i32 @uno_f32(float %a, float %b)
define i32 @true_f32(float %a, float %b) nounwind {
; ALL-LABEL: true_f32:
-; ALL: addiu $2, $zero, 1
+; 32-C: addiu $2, $zero, 1
+
+; 32-CMP: addiu $2, $zero, 1
+
+; 64-C: addiu $2, $zero, 1
+
+; 64-CMP: addiu $2, $zero, 1
+
+; MM-DAG: li16 $2, 1
%1 = fcmp true float %a, %b
%2 = zext i1 %1 to i32
@@ -376,7 +542,15 @@ define i32 @true_f32(float %a, float %b)
define i32 @false_f64(double %a, double %b) nounwind {
; ALL-LABEL: false_f64:
-; ALL: addiu $2, $zero, 0
+; 32-C: addiu $2, $zero, 0
+
+; 32-CMP: addiu $2, $zero, 0
+
+; 64-C: addiu $2, $zero, 0
+
+; 64-CMP: addiu $2, $zero, 0
+
+; MM-DAG: lui $2, 0
%1 = fcmp false double %a, %b
%2 = zext i1 %1 to i32
@@ -402,6 +576,16 @@ define i32 @oeq_f64(double %a, double %b
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.eq.d $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp oeq double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -426,6 +610,16 @@ define i32 @ogt_f64(double %a, double %b
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ule.d $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
+; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ogt double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -450,6 +644,16 @@ define i32 @oge_f64(double %a, double %b
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ult.d $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
+; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp oge double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -474,6 +678,16 @@ define i32 @olt_f64(double %a, double %b
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.olt.d $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp olt double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -498,6 +712,16 @@ define i32 @ole_f64(double %a, double %b
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ole.d $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ole double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -524,6 +748,17 @@ define i32 @one_f64(double %a, double %b
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ueq.d $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG: andi16 $2, $[[T2]], 1
+
%1 = fcmp one double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -550,6 +785,17 @@ define i32 @ord_f64(double %a, double %b
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.un.d $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG: andi16 $2, $[[T2]], 1
+
%1 = fcmp ord double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -574,6 +820,16 @@ define i32 @ueq_f64(double %a, double %b
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ueq.d $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ueq double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -598,6 +854,16 @@ define i32 @ugt_f64(double %a, double %b
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ole.d $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
+; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ugt double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -622,6 +888,16 @@ define i32 @uge_f64(double %a, double %b
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.olt.d $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
+; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp uge double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -646,6 +922,16 @@ define i32 @ult_f64(double %a, double %b
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ult.d $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ult double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -670,6 +956,16 @@ define i32 @ule_f64(double %a, double %b
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ule.d $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ule double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -696,6 +992,17 @@ define i32 @une_f64(double %a, double %b
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.eq.d $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG: andi16 $2, $[[T2]], 1
+
%1 = fcmp une double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -720,6 +1027,16 @@ define i32 @uno_f64(double %a, double %b
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.un.d $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp uno double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -727,7 +1044,15 @@ define i32 @uno_f64(double %a, double %b
define i32 @true_f64(double %a, double %b) nounwind {
; ALL-LABEL: true_f64:
-; ALL: addiu $2, $zero, 1
+; 32-C: addiu $2, $zero, 1
+
+; 32-CMP: addiu $2, $zero, 1
+
+; 64-C: addiu $2, $zero, 1
+
+; 64-CMP: addiu $2, $zero, 1
+
+; MM-DAG: li16 $2, 1
%1 = fcmp true double %a, %b
%2 = zext i1 %1 to i32
@@ -765,6 +1090,31 @@ entry:
; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
; 64-CMP-DAG: bnezc $[[T4]],
+; MM32R3-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12
+; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI32_0)
+; MM32R3-DAG: lwc1 $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])
+; MM32R3-DAG: c.ole.s $[[T0]], $[[T2]]
+; MM32R3-DAG: bc1t
+
+; MM32R6-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12
+; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI32_0)
+; MM32R6-DAG: lwc1 $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])
+; MM32R6-DAG: cmp.le.s $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
+; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3:f[0-9]+]]
+; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1
+; MM32R6-DAG: bnez $[[T5]],
+
+; MM64R6-DAG: lui $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f32)))
+; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25
+; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f32)))
+; MM64R6-DAG: add.s $[[T3:f[0-9]+]], $f13, $f12
+; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page($CPI32_0)($[[T2]])
+; MM64R6-DAG: lwc1 $[[T5:f[0-9]+]], %got_ofst($CPI32_0)($[[T4]])
+; MM64R6-DAG: cmp.le.s $[[T6:f[0-9]+]], $[[T3]], $[[T5]]
+; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]]
+; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1
+; MM64R6-DAG: bnez $[[T8]],
+
%add = fadd fast float %at, %angle
%cmp = fcmp ogt float %add, 1.000000e+00
br i1 %cmp, label %if.then, label %if.end
@@ -809,6 +1159,31 @@ entry:
; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
; 64-CMP-DAG: bnezc $[[T4]],
+; MM32R3-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12
+; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0)
+; MM32R3-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
+; MM32R3-DAG: c.ole.d $[[T0]], $[[T2]]
+; MM32R3-DAG: bc1t
+
+; MM32R6-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12
+; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0)
+; MM32R6-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
+; MM32R6-DAG: cmp.le.d $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
+; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3]]
+; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1
+; MM32R6-DAG: bnez $[[T5]],
+
+; MM64R6-DAG: lui $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f64)))
+; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25
+; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f64)))
+; MM64R6-DAG: add.d $[[T3:f[0-9]+]], $f13, $f12
+; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page($CPI33_0)($[[T2]])
+; MM64R6-DAG: ldc1 $[[T5:f[0-9]+]], %got_ofst($CPI33_0)($[[T4]])
+; MM64R6-DAG: cmp.le.d $[[T6:f[0-9]+]], $[[T3]], $[[T5]]
+; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]]
+; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1
+; MM64R6-DAG: bnez $[[T8]],
+
%add = fadd fast double %at, %angle
%cmp = fcmp ogt double %add, 1.000000e+00
br i1 %cmp, label %if.then, label %if.end
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll?rev=272256&r1=272255&r2=272256&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/select-dbl.ll Thu Jun 9 06:15:53 2016
@@ -13,7 +13,7 @@
; RUN: -check-prefix=ALL -check-prefix=CMOV \
; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
+; RUN: -check-prefix=ALL -check-prefix=SEL-32 -check-prefix=32R6
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
@@ -27,7 +27,11 @@
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
+; RUN: -check-prefix=ALL -check-prefix=SEL-64 -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM32R3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM32R6 -check-prefix=SEL-32
define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
entry:
@@ -71,6 +75,13 @@ entry:
; SEL-64: mtc1 $4, $f0
; SEL-64: sel.d $f0, $f14, $f13
+
+ ; MM32R3: mtc1 $7, $[[F0:f[0-9]+]]
+ ; MM32R3: mthc1 $6, $[[F0]]
+ ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MM32R3: ldc1 $f0, 16($sp)
+ ; MM32R3: movn.d $f0, $[[F0]], $[[T0]]
+
%r = select i1 %s, double %x, double %y
ret double %r
}
@@ -112,6 +123,12 @@ entry:
; SEL-64: mtc1 $6, $f0
; SEL-64: sel.d $f0, $f13, $f12
+
+ ; MM32R3: lw $[[T0:[0-9]+]], 16($sp)
+ ; MM32R3: andi16 $[[T1:[0-9]+]], $[[T0:[0-9]+]], 1
+ ; MM32R3: movn.d $f14, $f12, $[[T1]]
+ ; MM32R3: mov.d $f0, $f14
+
%r = select i1 %s, double %x, double %y
ret double %r
}
@@ -143,6 +160,11 @@ entry:
; SEL-64: cmp.lt.d $f0, $f12, $f13
; SEL-64: sel.d $f0, $f13, $f12
+
+ ; MM32R3: c.olt.d $f12, $f14
+ ; MM32R3: movt.d $f14, $f12, $fcc0
+ ; MM32R3: mov.d $f0, $f14
+
%s = fcmp olt double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
@@ -175,6 +197,11 @@ entry:
; SEL-64: cmp.le.d $f0, $f12, $f13
; SEL-64: sel.d $f0, $f13, $f12
+
+ ; MM32R3: c.ole.d $f12, $f14
+ ; MM32R3: movt.d $f14, $f12, $fcc0
+ ; MM32R3: mov.d $f0, $f14
+
%s = fcmp ole double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
@@ -207,6 +234,11 @@ entry:
; SEL-64: cmp.lt.d $f0, $f13, $f12
; SEL-64: sel.d $f0, $f13, $f12
+
+ ; MM32R3: c.ule.d $f12, $f14
+ ; MM32R3: movf.d $f14, $f12, $fcc0
+ ; MM32R3: mov.d $f0, $f14
+
%s = fcmp ogt double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
@@ -239,6 +271,11 @@ entry:
; SEL-64: cmp.le.d $f0, $f13, $f12
; SEL-64: sel.d $f0, $f13, $f12
+
+ ; MM32R3: c.ult.d $f12, $f14
+ ; MM32R3: movf.d $f14, $f12, $fcc0
+ ; MM32R3: mov.d $f0, $f14
+
%s = fcmp oge double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
@@ -271,6 +308,11 @@ entry:
; SEL-64: cmp.eq.d $f0, $f12, $f13
; SEL-64: sel.d $f0, $f13, $f12
+
+ ; MM32R3: c.eq.d $f12, $f14
+ ; MM32R3: movt.d $f14, $f12, $fcc0
+ ; MM32R3: mov.d $f0, $f14
+
%s = fcmp oeq double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
@@ -296,7 +338,8 @@ entry:
; SEL-32: cmp.ueq.d $f0, $f12, $f14
; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
- ; SEL-32: not $[[T0]], $[[T0]]
+ ; 32R6: not $[[T0]], $[[T0]]
+ ; MM32R6: nor $[[T0]], $[[T0]], $zero
; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
; SEL-32: sel.d $f0, $f14, $f12
@@ -309,6 +352,11 @@ entry:
; SEL-64: not $[[T0]], $[[T0]]
; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
; SEL-64: sel.d $f0, $f13, $f12
+
+ ; MM32R3: c.ueq.d $f12, $f14
+ ; MM32R3: movf.d $f14, $f12, $fcc0
+ ; MM32R3: mov.d $f0, $f14
+
%s = fcmp one double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll?rev=272256&r1=272255&r2=272256&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll Thu Jun 9 06:15:53 2016
@@ -13,7 +13,7 @@
; RUN: -check-prefix=ALL -check-prefix=CMOV \
; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
+; RUN: -check-prefix=ALL -check-prefix=SEL-32 -check-prefix=32R6
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
@@ -27,7 +27,11 @@
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
+; RUN: -check-prefix=ALL -check-prefix=SEL-64 -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM32R3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM32R6 -check-prefix=SEL-32
define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
entry:
@@ -60,6 +64,12 @@ entry:
; SEL-64: mtc1 $4, $f0
; SEL-64: sel.s $f0, $f14, $f13
+
+ ; MM32R3: mtc1 $6, $[[F0:f[0-9]+]]
+ ; MM32R3: mtc1 $5, $[[F1:f[0-9]+]]
+ ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MM32R3: movn.s $f0, $[[F1]], $[[T0]]
+
%r = select i1 %s, float %x, float %y
ret float %r
}
@@ -91,6 +101,11 @@ entry:
; SEL-64: mtc1 $6, $f0
; SEL-64: sel.s $f0, $f13, $f12
+
+ ; MM32R3: andi16 $[[T0:[0-9]+]], $6, 1
+ ; MM32R3: movn.s $[[F0:f[0-9]+]], $f12, $[[T0]]
+ ; MM32R3: mov.s $f0, $[[F0]]
+
%r = select i1 %s, float %x, float %y
ret float %r
}
@@ -122,6 +137,11 @@ entry:
; SEL-64: cmp.lt.s $f0, $f12, $f13
; SEL-64: sel.s $f0, $f13, $f12
+
+ ; MM32R3: c.olt.s $f12, $f14
+ ; MM32R3: movt.s $f14, $f12, $fcc0
+ ; MM32R3: mov.s $f0, $f14
+
%s = fcmp olt float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
@@ -154,6 +174,11 @@ entry:
; SEL-64: cmp.le.s $f0, $f12, $f13
; SEL-64: sel.s $f0, $f13, $f12
+
+ ; MM32R3: c.ole.s $f12, $f14
+ ; MM32R3: movt.s $f14, $f12, $fcc0
+ ; MM32R3: mov.s $f0, $f14
+
%s = fcmp ole float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
@@ -186,6 +211,11 @@ entry:
; SEL-64: cmp.lt.s $f0, $f13, $f12
; SEL-64: sel.s $f0, $f13, $f12
+
+ ; MM32R3: c.ule.s $f12, $f14
+ ; MM32R3: movf.s $f14, $f12, $fcc0
+ ; MM32R3: mov.s $f0, $f14
+
%s = fcmp ogt float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
@@ -218,6 +248,11 @@ entry:
; SEL-64: cmp.le.s $f0, $f13, $f12
; SEL-64: sel.s $f0, $f13, $f12
+
+ ; MM32R3: c.ult.s $f12, $f14
+ ; MM32R3: movf.s $f14, $f12, $fcc0
+ ; MM32R3: mov.s $f0, $f14
+
%s = fcmp oge float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
@@ -250,6 +285,11 @@ entry:
; SEL-64: cmp.eq.s $f0, $f12, $f13
; SEL-64: sel.s $f0, $f13, $f12
+
+ ; MM32R3: c.eq.s $f12, $f14
+ ; MM32R3: movt.s $f14, $f12, $fcc0
+ ; MM32R3: mov.s $f0, $f14
+
%s = fcmp oeq float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
@@ -275,7 +315,8 @@ entry:
; SEL-32: cmp.ueq.s $f0, $f12, $f14
; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
- ; SEL-32: not $[[T0]], $[[T0]]
+ ; 32R6: not $[[T0]], $[[T0]]
+ ; MM32R6: nor $[[T0]], $[[T0]], $zero
; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
; SEL-32: sel.s $f0, $f14, $f12
@@ -289,6 +330,10 @@ entry:
; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
; SEL-64: sel.s $f0, $f13, $f12
+ ; MM32R3: c.ueq.s $f12, $f14
+ ; MM32R3: movf.s $f14, $f12, $fcc0
+ ; MM32R3: mov.s $f0, $f14
+
%s = fcmp one float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/select-int.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/select-int.ll?rev=272256&r1=272255&r2=272256&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/select-int.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/select-int.ll Thu Jun 9 06:15:53 2016
@@ -28,6 +28,10 @@
; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM32R3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32R6
define signext i1 @tst_select_i1_i1(i1 signext %s,
i1 signext %x, i1 signext %y) {
@@ -50,6 +54,16 @@ entry:
; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
; SEL: or $2, $[[T2]], $[[T1]]
+
+ ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
+ ; MM32R3: move $2, $[[T1]]
+
+ ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
+ ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]]
+ ; MMR6: or $2, $[[T2]], $[[T1]]
+
%r = select i1 %s, i1 %x, i1 %y
ret i1 %r
}
@@ -75,6 +89,16 @@ entry:
; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
; SEL: or $2, $[[T2]], $[[T1]]
+
+ ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
+ ; MM32R3: move $2, $[[T1]]
+
+ ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
+ ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]]
+ ; MMR6: or $2, $[[T2]], $[[T1]]
+
%r = select i1 %s, i8 %x, i8 %y
ret i8 %r
}
@@ -100,6 +124,16 @@ entry:
; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
; SEL: or $2, $[[T2]], $[[T1]]
+
+ ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
+ ; MM32R3: move $2, $[[T1]]
+
+ ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
+ ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]]
+ ; MMR6: or $2, $[[T2]], $[[T1]]
+
%r = select i1 %s, i32 %x, i32 %y
ret i32 %r
}
@@ -157,6 +191,23 @@ entry:
; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
; SEL-64: selnez $[[T0]], $5, $[[T0]]
; SEL-64: or $2, $[[T0]], $[[T1]]
+
+ ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MM32R3: lw $2, 16($sp)
+ ; MM32R3: movn $2, $6, $[[T0]]
+ ; MM32R3: lw $3, 20($sp)
+ ; MM32R3: movn $3, $7, $[[T0]]
+
+ ; MM32R6: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MM32R6: lw $[[T1:[0-9]+]], 16($sp)
+ ; MM32R6: seleqz $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+ ; MM32R6: selnez $[[T3:[0-9]+]], $6, $[[T0]]
+ ; MM32R6: or $2, $[[T3]], $[[T2]]
+ ; MM32R6: lw $[[T4:[0-9]+]], 20($sp)
+ ; MM32R6: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]]
+ ; MM32R6: selnez $[[T6:[0-9]+]], $7, $[[T0]]
+ ; MM32R6: or $3, $[[T6]], $[[T5]]
+
%r = select i1 %s, i64 %x, i64 %y
ret i64 %r
}
@@ -164,47 +215,58 @@ entry:
define i8* @tst_select_word_cst(i8* %a, i8* %b) {
; ALL-LABEL: tst_select_word_cst:
- ; M2: addiu $1, $zero, -1
- ; M2: xor $1, $5, $1
- ; M2: sltu $1, $zero, $1
- ; M2: bnez $1, $[[BB0:BB[0-9_]+]]
+ ; M2: addiu $[[T0:[0-9]+]], $zero, -1
+ ; M2: xor $[[T1:[0-9]+]], $5, $[[T0]]
+ ; M2: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
+ ; M2: bnez $[[T2]], $[[BB0:BB[0-9_]+]]
; M2: addiu $2, $zero, 0
; M2: move $2, $4
; M2: $[[BB0]]:
; M2: jr $ra
- ; M3: daddiu $1, $zero, -1
- ; M3: xor $1, $5, $1
- ; M3: sltu $1, $zero, $1
- ; M3: bnez $1, $[[BB0:BB[0-9_]+]]
+ ; M3: daddiu $[[T0:[0-9]+]], $zero, -1
+ ; M3: xor $[[T1:[0-9]+]], $5, $[[T0]]
+ ; M3: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
+ ; M3: bnez $[[T2]], $[[BB0:BB[0-9_]+]]
; M3: daddiu $2, $zero, 0
; M3: move $2, $4
; M3: $[[BB0]]:
; M3: jr $ra
- ; CMOV-32: addiu $1, $zero, -1
- ; CMOV-32: xor $1, $5, $1
- ; CMOV-32: movn $4, $zero, $1
+ ; CMOV-32: addiu $[[T0:[0-9]+]], $zero, -1
+ ; CMOV-32: xor $[[T1:[0-9]+]], $5, $[[T0]]
+ ; CMOV-32: movn $[[T2:[0-9]+]], $zero, $[[T1]]
; CMOV-32: jr $ra
- ; CMOV-32: move $2, $4
+ ; CMOV-32: move $2, $[[T2]]
- ; SEL-32: addiu $1, $zero, -1
- ; SEL-32: xor $1, $5, $1
- ; SEL-32: sltu $1, $zero, $1
+ ; SEL-32: addiu $[[T0:[0-9]+]], $zero, -1
+ ; SEL-32: xor $[[T1:[0-9]+]], $5, $[[T0]]
+ ; SEL-32: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
; SEL-32: jr $ra
- ; SEL-32: seleqz $2, $4, $1
+ ; SEL-32: seleqz $2, $4, $[[T2]]
- ; CMOV-64: daddiu $1, $zero, -1
- ; CMOV-64: xor $1, $5, $1
- ; CMOV-64: movn $4, $zero, $1
- ; CMOV-64: move $2, $4
-
- ; SEL-64: daddiu $1, $zero, -1
- ; SEL-64: xor $1, $5, $1
- ; SEL-64: sltu $1, $zero, $1
+ ; CMOV-64: daddiu $[[T0:[0-9]+]], $zero, -1
+ ; CMOV-64: xor $[[T1:[0-9]+]], $5, $[[T0]]
+ ; CMOV-64: movn $[[T2:[0-9]+]], $zero, $[[T1]]
+ ; CMOV-64: move $2, $[[T2]]
+
+ ; SEL-64: daddiu $[[T0:[0-9]+]], $zero, -1
+ ; SEL-64: xor $[[T1:[0-9]+]], $5, $[[T0]]
+ ; SEL-64: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
; FIXME: This shift is redundant.
- ; SEL-64: sll $1, $1, 0
- ; SEL-64: seleqz $2, $4, $1
+ ; SEL-64: sll $[[T2]], $[[T2]], 0
+ ; SEL-64: seleqz $2, $4, $[[T2]]
+
+ ; MM32R3: li16 $[[T0:[0-9]+]], -1
+ ; MM32R3: xor $[[T1:[0-9]+]], $5, $[[T0]]
+ ; MM32R3: lui $[[T2:[0-9]+]], 0
+ ; MM32R3: movn $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+ ; MM32R3: move $2, $[[T3]]
+
+ ; MM32R6: li16 $[[T0:[0-9]+]], -1
+ ; MM32R6: xor $[[T1:[0-9]+]], $5, $[[T0]]
+ ; MM32R6: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
+ ; MM32R6: seleqz $2, $4, $[[T2]]
%cmp = icmp eq i8* %b, inttoptr (i64 -1 to i8*)
%r = select i1 %cmp, i8* %a, i8* null
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