[PATCH] D20769: [IPRA] Interprocedural Register Allocation - Analysis Passes

Mehdi AMINI via llvm-commits llvm-commits at lists.llvm.org
Wed Jun 8 21:01:31 PDT 2016


mehdi_amini added inline comments.

================
Comment at: lib/CodeGen/RegUsageInfoCollector.cpp:92
@@ +91,3 @@
+  const TargetMachine &TM = MF.getTarget();
+  const MCRegisterInfo *MCRI = TM.getMCRegisterInfo();
+
----------------
I think MatzeB mentioned that TRI is a subclass of MCRI, so I'm not sure why you're using MCRI at all while you have TRI.

================
Comment at: lib/CodeGen/RegUsageInfoCollector.cpp:123
@@ +122,3 @@
+  for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
+    if (!(RegMask[PReg / 32] & 1u << PReg % 32))
+      DEBUG(dbgs() << MCRI->getName(PReg) << " ");
----------------
Why aren't you using `MachineOperand::clobbersPhysReg` here?

================
Comment at: test/CodeGen/Generic/reg-usage-info.ll:8
@@ +7,3 @@
+define preserve_allcc void @foo()#0 {
+; CHECK: foo Clobbered Registers: EFLAGS YMM0 YMM1 YMM2 YMM3 YMM4 YMM5 YMM6 YMM7 YMM8 YMM9 YMM10 YMM11 YMM12 YMM13 YMM14 YMM15 ZMM0 ZMM1 ZMM2 ZMM3 ZMM4 ZMM5 ZMM6 ZMM7 ZMM8 ZMM9 ZMM10 ZMM11 ZMM12 ZMM13 ZMM14 ZMM15
+  call void @bar1()
----------------
What will be printed for bar1 and bar2? 
Add the CHECK lines here.


http://reviews.llvm.org/D20769





More information about the llvm-commits mailing list