[PATCH] D20931: [X86] Reduce the width of multiplification when its operands are extended from i8 or i16

[Eli Friedman via llvm-commits]

eli.friedman added inline comments.

================
Comment at: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:673
@@ -672,2 +672,3 @@
   case ISD::MUL:
+  case ISD::MULHU:
   case ISD::FADD:
----------------
Do you need MULHS here too?  (Maybe missing a test for this?)

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:26453
@@ +26452,3 @@
+      // If Opd is anyext(i8), we suppose the value range of Opd is 0 to 127,
+      // so we don't care whether anyext is either sext or zext.
+      if (Opd.getOperand(0).getValueType().getVectorElementType() == MVT::i8)
----------------
This comment is confusing; the operand isn't actually guaranteed to be between 0 and 127.  (The transform is safe because we can assume an appropriate number of leading sign/zero bits.)

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:26478
@@ +26477,3 @@
+        SignBits[i] = std::min(SignBits[i], DAG.ComputeNumSignBits(SubOp));
+      }
+    } else {
----------------
Probably better to use APInt::getNumSignBits here.


Repository:
  rL LLVM

http://reviews.llvm.org/D20931