[llvm] r272160 - [Target] Introduce a generic opcode for bitwise OR: G_OR.
Quentin Colombet via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 8 09:12:19 PDT 2016
Author: qcolombet
Date: Wed Jun 8 11:12:19 2016
New Revision: 272160
URL: http://llvm.org/viewvc/llvm-project?rev=272160&view=rev
Log:
[Target] Introduce a generic opcode for bitwise OR: G_OR.
This G_OR is used in GlobalISel to represent bitwise OR.
Modified:
llvm/trunk/include/llvm/Target/GenericOpcodes.td
llvm/trunk/include/llvm/Target/TargetOpcodes.def
llvm/trunk/test/TableGen/trydecode-emission.td
llvm/trunk/test/TableGen/trydecode-emission2.td
llvm/trunk/test/TableGen/trydecode-emission3.td
Modified: llvm/trunk/include/llvm/Target/GenericOpcodes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GenericOpcodes.td?rev=272160&r1=272159&r2=272160&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/GenericOpcodes.td (original)
+++ llvm/trunk/include/llvm/Target/GenericOpcodes.td Wed Jun 8 11:12:19 2016
@@ -12,6 +12,9 @@
//
//===----------------------------------------------------------------------===//
+//------------------------------------------------------------------------------
+// Binary ops.
+//------------------------------------------------------------------------------
// Generic addition.
def G_ADD : Instruction {
let OutOperandList = (outs unknown:$dst);
@@ -21,6 +24,18 @@ def G_ADD : Instruction {
let isCommutable = 1;
}
+// Generic bitwise or.
+def G_OR : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$src1, unknown:$src2);
+ let AsmString = "";
+ let hasSideEffects = 0;
+ let isCommutable = 1;
+}
+
+//------------------------------------------------------------------------------
+// Branches.
+//------------------------------------------------------------------------------
// Generic unconditional branch.
def G_BR : Instruction {
let OutOperandList = (outs);
Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.def?rev=272160&r1=272159&r2=272160&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOpcodes.def (original)
+++ llvm/trunk/include/llvm/Target/TargetOpcodes.def Wed Jun 8 11:12:19 2016
@@ -150,8 +150,11 @@ HANDLE_TARGET_OPCODE(PATCHABLE_OP, 23)
HANDLE_TARGET_OPCODE(G_ADD, 24)
HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD)
+/// Generic Bitwise-OR instruction.
+HANDLE_TARGET_OPCODE(G_OR, 25)
+
/// Generic BRANCH instruction. This is an unconditional branch.
-HANDLE_TARGET_OPCODE(G_BR, 25)
+HANDLE_TARGET_OPCODE(G_BR, 26)
// TODO: Add more generic opcodes as we move along.
Modified: llvm/trunk/test/TableGen/trydecode-emission.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/trydecode-emission.td?rev=272160&r1=272159&r2=272160&view=diff
==============================================================================
--- llvm/trunk/test/TableGen/trydecode-emission.td (original)
+++ llvm/trunk/test/TableGen/trydecode-emission.td Wed Jun 8 11:12:19 2016
@@ -36,8 +36,8 @@ def InstB : TestInstruction {
// CHECK: /* 0 */ MCD::OPC_ExtractField, 4, 4, // Inst{7-4} ...
// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValue, 0, 14, 0, // Skip to: 21
// CHECK-NEXT: /* 7 */ MCD::OPC_CheckField, 2, 2, 0, 5, 0, // Skip to: 18
-// CHECK-NEXT: /* 13 */ MCD::OPC_TryDecode, 27, 0, 0, 0, // Opcode: InstB, skip to: 18
-// CHECK-NEXT: /* 18 */ MCD::OPC_Decode, 26, 1, // Opcode: InstA
+// CHECK-NEXT: /* 13 */ MCD::OPC_TryDecode, 28, 0, 0, 0, // Opcode: InstB, skip to: 18
+// CHECK-NEXT: /* 18 */ MCD::OPC_Decode, 27, 1, // Opcode: InstA
// CHECK-NEXT: /* 21 */ MCD::OPC_Fail,
// CHECK: if (DecodeInstB(MI, insn, Address, Decoder) == MCDisassembler::Fail) { DecodeComplete = false; return MCDisassembler::Fail; }
Modified: llvm/trunk/test/TableGen/trydecode-emission2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/trydecode-emission2.td?rev=272160&r1=272159&r2=272160&view=diff
==============================================================================
--- llvm/trunk/test/TableGen/trydecode-emission2.td (original)
+++ llvm/trunk/test/TableGen/trydecode-emission2.td Wed Jun 8 11:12:19 2016
@@ -35,9 +35,9 @@ def InstB : TestInstruction {
// CHECK-NEXT: /* 7 */ MCD::OPC_ExtractField, 5, 3, // Inst{7-5} ...
// CHECK-NEXT: /* 10 */ MCD::OPC_FilterValue, 0, 22, 0, // Skip to: 36
// CHECK-NEXT: /* 14 */ MCD::OPC_CheckField, 0, 2, 3, 5, 0, // Skip to: 25
-// CHECK-NEXT: /* 20 */ MCD::OPC_TryDecode, 27, 0, 0, 0, // Opcode: InstB, skip to: 25
+// CHECK-NEXT: /* 20 */ MCD::OPC_TryDecode, 28, 0, 0, 0, // Opcode: InstB, skip to: 25
// CHECK-NEXT: /* 25 */ MCD::OPC_CheckField, 3, 2, 0, 5, 0, // Skip to: 36
-// CHECK-NEXT: /* 31 */ MCD::OPC_TryDecode, 26, 1, 0, 0, // Opcode: InstA, skip to: 36
+// CHECK-NEXT: /* 31 */ MCD::OPC_TryDecode, 27, 1, 0, 0, // Opcode: InstA, skip to: 36
// CHECK-NEXT: /* 36 */ MCD::OPC_Fail,
// CHECK: if (DecodeInstB(MI, insn, Address, Decoder) == MCDisassembler::Fail) { DecodeComplete = false; return MCDisassembler::Fail; }
Modified: llvm/trunk/test/TableGen/trydecode-emission3.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/trydecode-emission3.td?rev=272160&r1=272159&r2=272160&view=diff
==============================================================================
--- llvm/trunk/test/TableGen/trydecode-emission3.td (original)
+++ llvm/trunk/test/TableGen/trydecode-emission3.td Wed Jun 8 11:12:19 2016
@@ -37,8 +37,8 @@ def InstB : TestInstruction {
// CHECK: /* 0 */ MCD::OPC_ExtractField, 4, 4, // Inst{7-4} ...
// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValue, 0, 14, 0, // Skip to: 21
// CHECK-NEXT: /* 7 */ MCD::OPC_CheckField, 2, 2, 0, 5, 0, // Skip to: 18
-// CHECK-NEXT: /* 13 */ MCD::OPC_TryDecode, 27, 0, 0, 0, // Opcode: InstB, skip to: 18
-// CHECK-NEXT: /* 18 */ MCD::OPC_Decode, 26, 1, // Opcode: InstA
+// CHECK-NEXT: /* 13 */ MCD::OPC_TryDecode, 28, 0, 0, 0, // Opcode: InstB, skip to: 18
+// CHECK-NEXT: /* 18 */ MCD::OPC_Decode, 27, 1, // Opcode: InstA
// CHECK-NEXT: /* 21 */ MCD::OPC_Fail,
// CHECK: if (DecodeInstBOp(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { DecodeComplete = false; return MCDisassembler::Fail; }
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