[llvm] r272060 - [X86][SSE4A] Regenerated SSE4A intrinsics tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 7 14:15:45 PDT 2016
Author: rksimon
Date: Tue Jun 7 16:15:45 2016
New Revision: 272060
URL: http://llvm.org/viewvc/llvm-project?rev=272060&view=rev
Log:
[X86][SSE4A] Regenerated SSE4A intrinsics tests
There are no VEX encoded versions of SSE4A instructions, make sure that AVX targets give the same output
Modified:
llvm/trunk/test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll
llvm/trunk/test/CodeGen/X86/sse4a.ll
Modified: llvm/trunk/test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll?rev=272060&r1=272059&r2=272060&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll Tue Jun 7 16:15:45 2016
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=ALL --check-prefix=X32
-; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=ALL --check-prefix=X64
+; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-prefix=X64
; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse4a-builtins.c
Modified: llvm/trunk/test/CodeGen/X86/sse4a.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse4a.ll?rev=272060&r1=272059&r2=272060&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse4a.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse4a.ll Tue Jun 7 16:15:45 2016
@@ -1,9 +1,20 @@
-; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4a | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-unknown-linux -mattr=sse4a | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-prefix=X64
define void @test1(i8* %p, <4 x float> %a) nounwind optsize ssp {
-; CHECK-LABEL: test1:
-; CHECK: movntss
+; X32-LABEL: test1:
+; X32: # BB#0:
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movntss %xmm0, (%eax)
+; X32-NEXT: retl
+;
+; X64-LABEL: test1:
+; X64: # BB#0:
+; X64-NEXT: movntss %xmm0, (%rdi)
+; X64-NEXT: retq
tail call void @llvm.x86.sse4a.movnt.ss(i8* %p, <4 x float> %a) nounwind
ret void
}
@@ -11,8 +22,16 @@ define void @test1(i8* %p, <4 x float> %
declare void @llvm.x86.sse4a.movnt.ss(i8*, <4 x float>)
define void @test2(i8* %p, <2 x double> %a) nounwind optsize ssp {
-; CHECK-LABEL: test2:
-; CHECK: movntsd
+; X32-LABEL: test2:
+; X32: # BB#0:
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movntsd %xmm0, (%eax)
+; X32-NEXT: retl
+;
+; X64-LABEL: test2:
+; X64: # BB#0:
+; X64-NEXT: movntsd %xmm0, (%rdi)
+; X64-NEXT: retq
tail call void @llvm.x86.sse4a.movnt.sd(i8* %p, <2 x double> %a) nounwind
ret void
}
@@ -20,8 +39,15 @@ define void @test2(i8* %p, <2 x double>
declare void @llvm.x86.sse4a.movnt.sd(i8*, <2 x double>)
define <2 x i64> @test3(<2 x i64> %x) nounwind uwtable ssp {
-; CHECK-LABEL: test3:
-; CHECK: extrq
+; X32-LABEL: test3:
+; X32: # BB#0:
+; X32-NEXT: extrq $2, $3, %xmm0
+; X32-NEXT: retl
+;
+; X64-LABEL: test3:
+; X64: # BB#0:
+; X64-NEXT: extrq $2, $3, %xmm0
+; X64-NEXT: retq
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2)
ret <2 x i64> %1
}
@@ -29,8 +55,15 @@ define <2 x i64> @test3(<2 x i64> %x) no
declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind
define <2 x i64> @test4(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
-; CHECK-LABEL: test4:
-; CHECK: extrq
+; X32-LABEL: test4:
+; X32: # BB#0:
+; X32-NEXT: extrq %xmm1, %xmm0
+; X32-NEXT: retl
+;
+; X64-LABEL: test4:
+; X64: # BB#0:
+; X64-NEXT: extrq %xmm1, %xmm0
+; X64-NEXT: retq
%1 = bitcast <2 x i64> %y to <16 x i8>
%2 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %1) nounwind
ret <2 x i64> %2
@@ -39,8 +72,15 @@ define <2 x i64> @test4(<2 x i64> %x, <2
declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind
define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
-; CHECK-LABEL: test5:
-; CHECK: insertq
+; X32-LABEL: test5:
+; X32: # BB#0:
+; X32-NEXT: insertq $6, $5, %xmm1, %xmm0
+; X32-NEXT: retl
+;
+; X64-LABEL: test5:
+; X64: # BB#0:
+; X64-NEXT: insertq $6, $5, %xmm1, %xmm0
+; X64-NEXT: retq
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 5, i8 6)
ret <2 x i64> %1
}
@@ -48,8 +88,15 @@ define <2 x i64> @test5(<2 x i64> %x, <2
declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind
define <2 x i64> @test6(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
-; CHECK-LABEL: test6:
-; CHECK: insertq
+; X32-LABEL: test6:
+; X32: # BB#0:
+; X32-NEXT: insertq %xmm1, %xmm0
+; X32-NEXT: retl
+;
+; X64-LABEL: test6:
+; X64: # BB#0:
+; X64-NEXT: insertq %xmm1, %xmm0
+; X64-NEXT: retq
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind
ret <2 x i64> %1
}
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