[llvm] r272007 - [Thumb-1] Add optimized constant materialization for integers [256..512)
James Molloy via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 7 06:10:14 PDT 2016
Author: jamesm
Date: Tue Jun 7 08:10:14 2016
New Revision: 272007
URL: http://llvm.org/viewvc/llvm-project?rev=272007&view=rev
Log:
[Thumb-1] Add optimized constant materialization for integers [256..512)
We can materialize these integers using a MOV; ADDi8 pair.
Added:
llvm/trunk/test/CodeGen/Thumb/constants.ll
Modified:
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=272007&r1=272006&r2=272007&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Jun 7 08:10:14 2016
@@ -485,6 +485,7 @@ unsigned ARMDAGToDAGISel::ConstantMateri
if (Subtarget->isThumb()) {
if (Val <= 255) return 1; // MOV
if (Subtarget->hasV6T2Ops() && Val <= 0xffff) return 1; // MOVW
+ if (Val <= 511) return 2; // MOV + ADDi8
if (~Val <= 255) return 2; // MOV + MVN
if (ARM_AM::isThumbImmShiftedVal(Val)) return 2; // MOV + LSL
} else {
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=272007&r1=272006&r2=272007&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Jun 7 08:10:14 2016
@@ -66,6 +66,14 @@ def thumb_immshifted_shamt : SDNodeXForm
return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);
}]>;
+def imm256_511 : ImmLeaf<i32, [{
+ return Imm >= 256 && Imm < 512;
+}]>;
+
+def thumb_imm256_511_addend : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(N->getZExtValue() - 255, SDLoc(N), MVT::i32);
+}]>;
+
// Scaled 4 immediate.
def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
def t_imm0_1020s4 : Operand<i32> {
@@ -1489,6 +1497,10 @@ def : T1Pat<(i32 thumb_immshifted:$src),
def : T1Pat<(i32 imm0_255_comp:$src),
(tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
+def : T1Pat<(i32 imm256_511:$src),
+ (tADDi8 (tMOVi8 255),
+ (thumb_imm256_511_addend imm:$src))>;
+
// Pseudo instruction that combines ldr from constpool and add pc. This should
// be expanded into two instructions late to allow if-conversion and
// scheduling.
Added: llvm/trunk/test/CodeGen/Thumb/constants.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/constants.ll?rev=272007&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/constants.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb/constants.ll Tue Jun 7 08:10:14 2016
@@ -0,0 +1,11 @@
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=cortex-m0 -verify-machineinstrs | FileCheck --check-prefix CHECK-T1 %s
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=cortex-m3 -verify-machineinstrs | FileCheck --check-prefix CHECK-T2 %s
+
+; CHECK-T1-LABEL: @mov_and_add
+; CHECK-T2-LABEL: @mov_and_add
+; CHECK-T1: movs r0, #255
+; CHECK-T1: adds r0, #12
+; CHECK-T2: movw r0, #267
+define i32 @mov_and_add() {
+ ret i32 267
+}
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