[PATCH] D21029: Support expanding partial-word cmpxchg to full-word cmpxchg in AtomicExpandPass.

[James Y Knight via llvm-commits]

jyknight created this revision.
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Many CPUs only have 4-byte cmpxchg, and not 1/2-byte instructions. For
those, you need to mask and shift appropriately and use a 4-byte
cmpxchg.

This change adds support for cmpxchg-based instruction sets (only SPARC,
in LLVM). The support can be extended for LL/SC-based instruction
sets (e.g. PPC and MIPS) in the future, supplanting the ISel expansions
those architectures currently use.

Tests added for SPARCv9.

http://reviews.llvm.org/D21029

Files:
  include/llvm/Target/TargetLowering.h
  lib/CodeGen/AtomicExpandPass.cpp
  lib/CodeGen/TargetLoweringBase.cpp
  lib/Target/Sparc/SparcISelLowering.cpp
  test/CodeGen/SPARC/atomics.ll
  test/Transforms/AtomicExpand/SPARC/partword.ll

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