[PATCH] D16917: [mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions

[Simon Dardis via llvm-commits]

sdardis requested changes to this revision.
sdardis added a comment.
This revision now requires changes to proceed.

Some nits and one minor change+addition.

For convenience, mips64 assemblers treat instructions like drotr as taking an immediate value in the range of 0..63 and then picking the d<op>32 form if required.

You will need to modify MipsMCCodeEmitter::encodeInstruction to do this.


================
Comment at: lib/Target/Mips/MicroMips64r6InstrInfo.td:250-251
@@ +249,4 @@
+class DSRA32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsra32", uimm5, II_DSRA32>;
+class DROTR_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr", uimm5, II_DROTR,
+                                                  rotr, immZExt5>;
+class DROTR32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr32", uimm5,
----------------
Like DSLL_, DSRA_, DROTR_MM64R6_DESC should take a uimm6 & immZExt6.

You will then have to modify MipsMCCodeEmitter::encodeInstruction & LowerLargeShift as well to pick the correct D<op> or D<op>32.

================
Comment at: lib/Target/Mips/Mips64InstrInfo.td:165-179
@@ -164,15 +164,17 @@
              SRA_FM<0x3e, 0>, ISA_MIPS3;
 let AdditionalPredicates = [NotInMicroMips] in {
   def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
                SRA_FM<0x3f, 0>, ISA_MIPS3;
 }
 
 // Rotate Instructions
-def DROTR  : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
-                              immZExt6>,
-             SRA_FM<0x3a, 1>, ISA_MIPS64R2;
-def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
-             SRLV_FM<0x16, 1>, ISA_MIPS64R2;
-def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
-              SRA_FM<0x3e, 1>, ISA_MIPS64R2;
+let AdditionalPredicates = [NotInMicroMips] in {
+  def DROTR  : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
+                                immZExt6>,
+               SRA_FM<0x3a, 1>, ISA_MIPS64R2;
+  def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
+               SRLV_FM<0x16, 1>, ISA_MIPS64R2;
+  def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
+                SRA_FM<0x3e, 1>, ISA_MIPS64R2;
+}
 
----------------
Join these two blocks together.

================
Comment at: lib/Target/Mips/Mips64InstrInfo.td:286-288
@@ -282,3 +285,5 @@
+             ISA_MIPS64_NOT_64R6;
+}
 /// Double Word Swap Bytes/HalfWords
 let AdditionalPredicates = [NotInMicroMips] in {
   def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
----------------
These two blocks can also be joined together.

================
Comment at: lib/Target/Mips/Mips64r6InstrInfo.td:103-113
@@ -102,11 +102,13 @@
 }
 def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
-def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
-def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
+  def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
+  def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
+}
 let AdditionalPredicates = [NotInMicroMips] in {
   def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
   def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
   def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
   def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
 }
 def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
----------------
Join these two block together.

================
Comment at: test/CodeGen/Mips/mips64shift.ll:100-101
@@ -98,3 +99,4 @@
 entry:
-; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
+; MIPS:       drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
+; MICROMIPS:  drotrv ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
   %shl = shl i64 %a0, 10
----------------
Once the above change is made, this can be simplified back to drotr $... 54.


http://reviews.llvm.org/D16917