[PATCH] D20951: [RFC][ARM][LLD] Initial support for ARM in lld

[Rui Ueyama via llvm-commits]

ruiu added inline comments.

================
Comment at: ELF/Target.cpp:1466
@@ +1465,3 @@
+  case R_ARM_JUMP24:
+    return S.isPreemptible() ? R_PLT_PC : R_PC;
+  case R_ARM_GOTOFF32:
----------------
I doubt this is correct. I'd think you want to return just R_PLT_PC and let adjustExpr in Relocations.cpp to relax it later.

================
Comment at: ELF/Target.cpp:1538-1542
@@ +1537,7 @@
+  case R_ARM_GOTOFF32:
+  case R_ARM_GOT_PREL:
+  case R_ARM_GOT_BREL:
+  case R_ARM_BASE_PREL:
+  case R_ARM_ABS32:
+  case R_ARM_REL32:
+    write32le(Loc, Val);
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Sort

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Comment at: ELF/Target.cpp:1549-1552
@@ +1548,6 @@
+    break;
+  case R_ARM_PC24:
+  case R_ARM_PLT32:
+  case R_ARM_CALL:
+  case R_ARM_JUMP24:
+    checkInt<26>(Val, Type);
----------------
Sort

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Comment at: ELF/Target.cpp:1575-1579
@@ +1574,7 @@
+    return 0;
+  case R_ARM_GOTOFF32:
+  case R_ARM_GOT_PREL:
+  case R_ARM_GOT_BREL:
+  case R_ARM_BASE_PREL:
+  case R_ARM_ABS32:
+    return SignExtend64<32>(read32le(Buf));
----------------
Sort

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Comment at: ELF/Target.cpp:1583
@@ +1582,3 @@
+  case R_ARM_PREL31:
+    return SignExtend64<31>(read32le(Buf) & ~0x80000000);
+    break;
----------------
Do you have to clear the most significant bit? I think SignExtend64<31> will do that for you.

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Comment at: ELF/Target.cpp:1596
@@ +1595,3 @@
+    // MOVT is in the range -32768 <= A < 32768
+    int64_t Val = read32le(Buf) & 0x000f0fff;
+    return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff));
----------------
Use uint64_t instead of int64_t to avoid confusion on right shift.


http://reviews.llvm.org/D20951