[PATCH] D21013: [KNL] Fix UMULO lowering.

Igor Breger via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 6 00:42:48 PDT 2016


igorb created this revision.
igorb added a reviewer: delena.
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igorb set the repository for this revision to rL LLVM.

[KNL] Fix UMULO lowering.  [[ https://llvm.org/bugs/show_bug.cgi?id=27873 | bug27873 ]]

Repository:
  rL LLVM

http://reviews.llvm.org/D21013

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/xaluo.ll

Index: test/CodeGen/X86/xaluo.ll
===================================================================
--- test/CodeGen/X86/xaluo.ll
+++ test/CodeGen/X86/xaluo.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple=x86_64-darwin-unknown                             < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
 ; RUN: llc -mtriple=x86_64-darwin-unknown -fast-isel -fast-isel-abort=1 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
-
+; RUN: llc -mtriple=x86_64-darwin-unknown -mcpu=knl < %s | FileCheck %s --check-prefix=KNL
 ;
 ; Get the actual value of the overflow bit.
 ;
@@ -734,6 +734,53 @@
   ret i1 true
 }
 
+ at b = external global [10 x [10 x i32]], align 16
+
+define void @bug27873(i64 %c1, i1 %c2) {
+; KNL-LABEL: bug27873:
+; KNL:       ## BB#0: ## %entry
+; KNL-NEXT:    andl $1, %esi
+; KNL-NEXT:    movl $160, %ecx
+; KNL-NEXT:    xorl %eax, %eax
+; KNL-NEXT:    mulq %rcx
+; KNL-NEXT:    kmovw %esi, %k0
+; KNL-NEXT:    seto %al
+; KNL-NEXT:    movl $360, %ecx ## imm = 0x168
+; KNL-NEXT:    addq _b@{{.*}}(%rip), %rcx
+; KNL-NEXT:    cmpq %rcx, %rdi
+; KNL-NEXT:    setb %cl
+; KNL-NEXT:    andl $1, %ecx
+; KNL-NEXT:    kmovw %ecx, %k1
+; KNL-NEXT:    kmovw %eax, %k2
+; KNL-NEXT:    korw %k2, %k1, %k1
+; KNL-NEXT:    korw %k1, %k0, %k0
+; KNL-NEXT:    kmovw %k0, %eax
+; KNL-NEXT:    andl $1, %eax
+; KNL-NEXT:    .p2align 4, 0x90
+; KNL-NEXT:  LBB55_1: ## %for.cond.us
+; KNL-NEXT:    ## =>This Inner Loop Header: Depth=1
+; KNL-NEXT:    testb %al, %al
+; KNL-NEXT:    jne LBB55_1
+; KNL-NEXT:  ## BB#2: ## %vector.body
+entry:
+  %mul = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 0, i64 160)
+  %mul.overflow = extractvalue { i64, i1 } %mul, 1
+  %0 = icmp ult i64 %c1, ptrtoint (i32* getelementptr inbounds ([10 x [10 x i32]], [10 x [10 x i32]]* @b, i64 0, i64 9, i64 0) to i64)
+  %1 = or i1 %0, %mul.overflow
+  %2 = or i1 false, %1
+  br label %for.cond.us
+
+for.cond.us:                                      ; preds = %scalar.ph, %entry
+  %brmerge1 = or i1 %c2, %2
+  br i1 %brmerge1, label %scalar.ph, label %vector.body
+
+vector.body:                                      ; preds = %for.cond.us
+  unreachable
+
+scalar.ph:                                        ; preds = %for.cond.us
+  br label %for.cond.us
+}
+
 declare {i8,  i1} @llvm.sadd.with.overflow.i8 (i8,  i8 ) nounwind readnone
 declare {i16, i1} @llvm.sadd.with.overflow.i16(i16, i16) nounwind readnone
 declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -20299,7 +20299,7 @@
     SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
 
     SDValue SetCC =
-      DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
+      DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
                   DAG.getConstant(X86::COND_O, DL, MVT::i32),
                   SDValue(Sum.getNode(), 2));
 


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