[llvm] r271797 - X86: enable TLS on Windows itanium

[Saleem Abdulrasool via llvm-commits]

Author: compnerd
Date: Sat Jun  4 13:27:22 2016
New Revision: 271797

URL: http://llvm.org/viewvc/llvm-project?rev=271797&view=rev
Log:
X86: enable TLS on Windows itanium

Windows itanium is nearly identical to windows-msvc (MS ABI for C, itanium for
C++).  Enable the TLS support for the target similar to the MSVC model.

Added:
    llvm/trunk/test/CodeGen/X86/tls-windows-itanium.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=271797&r1=271796&r2=271797&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Jun  4 13:27:22 2016
@@ -12975,6 +12975,7 @@ X86TargetLowering::LowerGlobalTLSAddress
   }
 
   if (Subtarget.isTargetKnownWindowsMSVC() ||
+      Subtarget.isTargetWindowsItanium() ||
       Subtarget.isTargetWindowsGNU()) {
     // Just use the implicit TLS architecture
     // Need to generate someting similar to:

Added: llvm/trunk/test/CodeGen/X86/tls-windows-itanium.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tls-windows-itanium.ll?rev=271797&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tls-windows-itanium.ll (added)
+++ llvm/trunk/test/CodeGen/X86/tls-windows-itanium.ll Sat Jun  4 13:27:22 2016
@@ -0,0 +1,30 @@
+; RUN: llc -mtriple i686-windows-itanium -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-ASM
+; RUN: llc -mtriple i686-windows-itanium -filetype obj -o - %s | llvm-readobj -relocations - | FileCheck %s -check-prefix CHECK-OBJ
+
+ at get_count_incremented.count = internal thread_local unnamed_addr global i32 0, align 4
+
+define i32 @get_count_incremented() {
+entry:
+  %0 = load i32, i32* @get_count_incremented.count, align 4
+  %inc = add i32 %0, 1
+  store i32 %inc, i32* @get_count_incremented.count, align 4
+  ret i32 %inc
+}
+
+; CHECK-ASM-LABEL: _get_count_incremented:
+; CHECK-ASM: movl __tls_index, %eax
+; CHECK-ASM: movl %fs:__tls_array, %ecx
+; CHECK-ASM: movl (%ecx,%eax,4), %ecx
+; CHECK-ASM: _get_count_incremented.count at SECREL32(%ecx), %eax
+; CHECK-ASM: incl %eax
+; CHECK-ASM: movl %eax, _get_count_incremented.count at SECREL32(%ecx)
+; CHECK-ASM: retl
+
+; CHECK-OBJ: Relocations [
+; CHECK-OBJ:   Section ({{[0-9]+}}) .text {
+; CHECK-OBJ:     0x1 IMAGE_REL_I386_DIR32 __tls_index
+; CHECK-OBJ:     0x8 IMAGE_REL_I386_DIR32 __tls_array
+; CHECK-OBJ:     0x11 IMAGE_REL_I386_SECREL _get_count_incremented.count
+; CHECK-OBJ:     0x18 IMAGE_REL_I386_SECREL _get_count_incremented.count
+; CHECK-OBJ:   }
+; CHECK-OBJ: ]