[llvm] r271658 - [mips] EABI CodeGen is completely untested and seems to have bitrotted. Remove it.
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 3 03:38:10 PDT 2016
Author: dsanders
Date: Fri Jun 3 05:38:09 2016
New Revision: 271658
URL: http://llvm.org/viewvc/llvm-project?rev=271658&view=rev
Log:
[mips] EABI CodeGen is completely untested and seems to have bitrotted. Remove it.
Summary:
There are no tests*, no EABI buildbots, and simple test cases do not work.
* There is a single MIPS16 test using a mips*-gnueabi triple but this test
doesn't test EABI and the triple doesn't cause EABI to be used.
Reviewers: sdardis
Subscribers: tberghammer, danalbert, srhines, dsanders, sdardis, llvm-commits
Differential Revision: http://reviews.llvm.org/D20906
Modified:
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
llvm/trunk/lib/Target/Mips/MipsCallingConv.td
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
llvm/trunk/lib/Target/Mips/MipsSubtarget.h
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp?rev=271658&r1=271657&r2=271658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp Fri Jun 3 05:38:09 2016
@@ -42,7 +42,7 @@ ArrayRef<MCPhysReg> MipsABIInfo::GetVarA
unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const {
if (IsO32())
return CC != CallingConv::Fast ? 16 : 0;
- if (IsN32() || IsN64() || IsEABI())
+ if (IsN32() || IsN64())
return 0;
llvm_unreachable("Unhandled ABI");
}
@@ -55,8 +55,6 @@ MipsABIInfo MipsABIInfo::computeTargetAB
return MipsABIInfo::N32();
else if (Options.getABIName().startswith("n64"))
return MipsABIInfo::N64();
- else if (Options.getABIName().startswith("eabi"))
- return MipsABIInfo::EABI();
else if (!Options.getABIName().empty())
llvm_unreachable("Unknown ABI option for MIPS");
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h?rev=271658&r1=271657&r2=271658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h Fri Jun 3 05:38:09 2016
@@ -23,7 +23,7 @@ class TargetRegisterClass;
class MipsABIInfo {
public:
- enum class ABI { Unknown, O32, N32, N64, EABI };
+ enum class ABI { Unknown, O32, N32, N64 };
protected:
ABI ThisABI;
@@ -35,7 +35,6 @@ public:
static MipsABIInfo O32() { return MipsABIInfo(ABI::O32); }
static MipsABIInfo N32() { return MipsABIInfo(ABI::N32); }
static MipsABIInfo N64() { return MipsABIInfo(ABI::N64); }
- static MipsABIInfo EABI() { return MipsABIInfo(ABI::EABI); }
static MipsABIInfo computeTargetABI(const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
@@ -43,7 +42,6 @@ public:
bool IsO32() const { return ThisABI == ABI::O32; }
bool IsN32() const { return ThisABI == ABI::N32; }
bool IsN64() const { return ThisABI == ABI::N64; }
- bool IsEABI() const { return ThisABI == ABI::EABI; }
ABI GetEnumValue() const { return ThisABI; }
/// The registers to use for byval arguments.
Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=271658&r1=271657&r2=271658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Fri Jun 3 05:38:09 2016
@@ -313,7 +313,6 @@ const char *MipsAsmPrinter::getCurrentAB
case MipsABIInfo::ABI::O32: return "abi32";
case MipsABIInfo::ABI::N32: return "abiN32";
case MipsABIInfo::ABI::N64: return "abi64";
- case MipsABIInfo::ABI::EABI: return "eabi32"; // TODO: handle eabi64
default: llvm_unreachable("Unknown Mips ABI");
}
}
@@ -713,15 +712,6 @@ void MipsAsmPrinter::EmitStartOfAsmFile(
// TODO: handle O64 ABI
- if (ABI.IsEABI()) {
- if (STI.isGP32bit())
- OutStreamer->SwitchSection(OutContext.getELFSection(".gcc_compiled_long32",
- ELF::SHT_PROGBITS, 0));
- else
- OutStreamer->SwitchSection(OutContext.getELFSection(".gcc_compiled_long64",
- ELF::SHT_PROGBITS, 0));
- }
-
TS.updateABIInfo(STI);
// We should always emit a '.module fp=...' but binutils 2.24 does not accept
Modified: llvm/trunk/lib/Target/Mips/MipsCallingConv.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCallingConv.td?rev=271658&r1=271657&r2=271658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsCallingConv.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsCallingConv.td Fri Jun 3 05:38:09 2016
@@ -212,48 +212,6 @@ def RetCC_MipsN : CallingConv<[
]>;
//===----------------------------------------------------------------------===//
-// Mips EABI Calling Convention
-//===----------------------------------------------------------------------===//
-
-def CC_MipsEABI : CallingConv<[
- // Promote i8/i16 arguments to i32.
- CCIfType<[i8, i16], CCPromoteToType<i32>>,
-
- // Integer arguments are passed in integer registers.
- CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
-
- // Single fp arguments are passed in pairs within 32-bit mode
- CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
- CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
-
- CCIfType<[f32], CCIfSubtargetNot<"isSingleFloat()",
- CCAssignToReg<[F12, F14, F16, F18]>>>,
-
- // The first 4 double fp arguments are passed in single fp registers.
- CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()",
- CCAssignToReg<[D6, D7, D8, D9]>>>,
-
- // Integer values get stored in stack slots that are 4 bytes in
- // size and 4-byte aligned.
- CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
-
- // Integer values get stored in stack slots that are 8 bytes in
- // size and 8-byte aligned.
- CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToStack<8, 8>>>
-]>;
-
-def RetCC_MipsEABI : CallingConv<[
- // i32 are returned in registers V0, V1
- CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
-
- // f32 are returned in registers F0, F1
- CCIfType<[f32], CCAssignToReg<[F0, F1]>>,
-
- // f64 are returned in register D0
- CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToReg<[D0]>>>
-]>;
-
-//===----------------------------------------------------------------------===//
// Mips FastCC Calling Convention
//===----------------------------------------------------------------------===//
def CC_MipsO32_FastCC : CallingConv<[
@@ -325,7 +283,6 @@ def CC_Mips_FastCC : CallingConv<[
// Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
- CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
CCDelegateTo<CC_MipsN_FastCC>
]>;
@@ -335,7 +292,6 @@ def CC_Mips_FastCC : CallingConv<[
//===----------------------------------------------------------------------===//
def RetCC_Mips : CallingConv<[
- CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
CCDelegateTo<RetCC_MipsO32>
@@ -377,8 +333,6 @@ def CC_Mips_FixedArg : CallingConv<[
CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>,
- // FIXME: There wasn't an EABI case in the original code and it seems unlikely
- // that it's the same as CC_MipsN
CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
CCDelegateTo<CC_MipsN>
]>;
@@ -386,8 +340,6 @@ def CC_Mips_FixedArg : CallingConv<[
def CC_Mips_VarArg : CallingConv<[
CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
- // FIXME: There wasn't an EABI case in the original code and it seems unlikely
- // that it's the same as CC_MipsN_VarArg
CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
CCDelegateTo<CC_MipsN_VarArg>
]>;
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=271658&r1=271657&r2=271658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Fri Jun 3 05:38:09 2016
@@ -2670,7 +2670,6 @@ MipsTargetLowering::LowerCall(TargetLowe
DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
getPointerTy(DAG.getDataLayout()));
- // With EABI is it possible to have 16 args on registers.
std::deque< std::pair<unsigned, SDValue> > RegsToPass;
SmallVector<SDValue, 8> MemOpChains;
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=271658&r1=271657&r2=271658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Fri Jun 3 05:38:09 2016
@@ -90,7 +90,7 @@ MipsSubtarget::MipsSubtarget(const Tripl
report_fatal_error("Code generation for MIPS-V is not implemented", false);
// Check if Architecture and ABI are compatible.
- assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
+ assert(((!isGP64bit() && isABI_O32()) ||
(isGP64bit() && (isABI_N32() || isABI_N64()))) &&
"Invalid Arch & ABI pair.");
@@ -164,7 +164,6 @@ Reloc::Model MipsSubtarget::getRelocatio
return TM.getRelocationModel();
}
-bool MipsSubtarget::isABI_EABI() const { return getABI().IsEABI(); }
bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=271658&r1=271657&r2=271658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Fri Jun 3 05:38:09 2016
@@ -163,8 +163,6 @@ public:
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
- /// Only O32 and EABI supported right now.
- bool isABI_EABI() const;
bool isABI_N64() const;
bool isABI_N32() const;
bool isABI_O32() const;
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