[llvm] r271629 - [AVX512] Ensure EVEX vpshufd, vpshuflw, and vpshufhw have isel priority over the VEX encoded ones.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 2 22:31:04 PDT 2016
Author: ctopper
Date: Fri Jun 3 00:31:04 2016
New Revision: 271629
URL: http://llvm.org/viewvc/llvm-project?rev=271629&view=rev
Log:
[AVX512] Ensure EVEX vpshufd, vpshuflw, and vpshufhw have isel priority over the VEX encoded ones.
Modified:
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll
llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=271629&r1=271628&r2=271629&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Jun 3 00:31:04 2016
@@ -4211,8 +4211,8 @@ defm PCMPGTD : PDI_binop_all<0x66, "pcmp
let ExeDomain = SSEPackedInt in {
multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
- SDNode OpNode> {
-let Predicates = [HasAVX] in {
+ SDNode OpNode, Predicate prd> {
+let Predicates = [HasAVX, prd] in {
def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, u8imm:$src2),
!strconcat("v", OpcodeStr,
@@ -4230,7 +4230,7 @@ let Predicates = [HasAVX] in {
Sched<[WriteShuffleLd]>;
}
-let Predicates = [HasAVX2] in {
+let Predicates = [HasAVX2, prd] in {
def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
(ins VR256:$src1, u8imm:$src2),
!strconcat("v", OpcodeStr,
@@ -4268,9 +4268,11 @@ let Predicates = [UseSSE2] in {
}
} // ExeDomain = SSEPackedInt
-defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
-defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
-defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
+defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd, NoVLX>, PD;
+defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw,
+ NoVLX_Or_NoBWI>, XS;
+defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw,
+ NoVLX_Or_NoBWI>, XD;
let Predicates = [HasAVX] in {
def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
Modified: llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll?rev=271629&r1=271628&r2=271629&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll Fri Jun 3 00:31:04 2016
@@ -5990,7 +5990,7 @@ define <8 x i16>@test_int_x86_avx512_mas
; CHECK-NEXT: ## xmm1 = xmm1[0,1,2,3,7,4,4,4]
; CHECK-NEXT: vpshufhw $3, %xmm0, %xmm2 {%k1} {z} ## encoding: [0x62,0xf1,0x7e,0x89,0x70,0xd0,0x03]
; CHECK-NEXT: ## xmm2 = k1[0,1,2,3,7,4,4,4]
-; CHECK-NEXT: vpshufhw $3, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x70,0xc0,0x03]
+; CHECK-NEXT: vpshufhw $3, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7e,0x08,0x70,0xc0,0x03]
; CHECK-NEXT: ## xmm0 = xmm0[0,1,2,3,7,4,4,4]
; CHECK-NEXT: vpaddw %xmm2, %xmm1, %xmm1 ## encoding: [0x62,0xf1,0x75,0x08,0xfd,0xca]
; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ## encoding: [0x62,0xf1,0x75,0x08,0xfd,0xc0]
@@ -6013,7 +6013,7 @@ define <16 x i16>@test_int_x86_avx512_ma
; CHECK-NEXT: ## ymm1 = ymm1[0,1,2,3,7,4,4,4,8,9,10,11,15,12,12,12]
; CHECK-NEXT: vpshufhw $3, %ymm0, %ymm2 {%k1} {z} ## encoding: [0x62,0xf1,0x7e,0xa9,0x70,0xd0,0x03]
; CHECK-NEXT: ## ymm2 = k1[0,1,2,3,7,4,4,4,8,9,10,11,15,12,12,12]
-; CHECK-NEXT: vpshufhw $3, %ymm0, %ymm0 ## encoding: [0xc5,0xfe,0x70,0xc0,0x03]
+; CHECK-NEXT: vpshufhw $3, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7e,0x28,0x70,0xc0,0x03]
; CHECK-NEXT: ## ymm0 = ymm0[0,1,2,3,7,4,4,4,8,9,10,11,15,12,12,12]
; CHECK-NEXT: vpaddw %ymm2, %ymm1, %ymm1 ## encoding: [0x62,0xf1,0x75,0x28,0xfd,0xca]
; CHECK-NEXT: vpaddw %ymm0, %ymm1, %ymm0 ## encoding: [0x62,0xf1,0x75,0x28,0xfd,0xc0]
@@ -6036,7 +6036,7 @@ define <8 x i16>@test_int_x86_avx512_mas
; CHECK-NEXT: ## xmm1 = xmm1[3,0,0,0,4,5,6,7]
; CHECK-NEXT: vpshuflw $3, %xmm0, %xmm2 {%k1} {z} ## encoding: [0x62,0xf1,0x7f,0x89,0x70,0xd0,0x03]
; CHECK-NEXT: ## xmm2 = k1[3,0,0,0,4,5,6,7]
-; CHECK-NEXT: vpshuflw $3, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x70,0xc0,0x03]
+; CHECK-NEXT: vpshuflw $3, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7f,0x08,0x70,0xc0,0x03]
; CHECK-NEXT: ## xmm0 = xmm0[3,0,0,0,4,5,6,7]
; CHECK-NEXT: vpaddw %xmm2, %xmm1, %xmm1 ## encoding: [0x62,0xf1,0x75,0x08,0xfd,0xca]
; CHECK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ## encoding: [0x62,0xf1,0x75,0x08,0xfd,0xc0]
@@ -6059,7 +6059,7 @@ define <16 x i16>@test_int_x86_avx512_ma
; CHECK-NEXT: ## ymm1 = ymm1[3,0,0,0,4,5,6,7,11,8,8,8,12,13,14,15]
; CHECK-NEXT: vpshuflw $3, %ymm0, %ymm2 {%k1} {z} ## encoding: [0x62,0xf1,0x7f,0xa9,0x70,0xd0,0x03]
; CHECK-NEXT: ## ymm2 = k1[3,0,0,0,4,5,6,7,11,8,8,8,12,13,14,15]
-; CHECK-NEXT: vpshuflw $3, %ymm0, %ymm0 ## encoding: [0xc5,0xff,0x70,0xc0,0x03]
+; CHECK-NEXT: vpshuflw $3, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7f,0x28,0x70,0xc0,0x03]
; CHECK-NEXT: ## ymm0 = ymm0[3,0,0,0,4,5,6,7,11,8,8,8,12,13,14,15]
; CHECK-NEXT: vpaddw %ymm2, %ymm1, %ymm1 ## encoding: [0x62,0xf1,0x75,0x28,0xfd,0xca]
; CHECK-NEXT: vpaddw %ymm0, %ymm1, %ymm0 ## encoding: [0x62,0xf1,0x75,0x28,0xfd,0xc0]
Modified: llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll?rev=271629&r1=271628&r2=271629&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll Fri Jun 3 00:31:04 2016
@@ -9555,7 +9555,7 @@ define <4 x i32>@test_int_x86_avx512_mas
; CHECK-NEXT: ## xmm1 = xmm1[3,0,0,0]
; CHECK-NEXT: vpshufd $3, %xmm0, %xmm2 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0x70,0xd0,0x03]
; CHECK-NEXT: ## xmm2 = k1[3,0,0,0]
-; CHECK-NEXT: vpshufd $3, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x70,0xc0,0x03]
+; CHECK-NEXT: vpshufd $3, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0x70,0xc0,0x03]
; CHECK-NEXT: ## xmm0 = xmm0[3,0,0,0]
; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1 ## encoding: [0x62,0xf1,0x75,0x08,0xfe,0xca]
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ## encoding: [0x62,0xf1,0x75,0x08,0xfe,0xc0]
@@ -9578,7 +9578,7 @@ define <8 x i32>@test_int_x86_avx512_mas
; CHECK-NEXT: ## ymm1 = ymm1[3,0,0,0,7,4,4,4]
; CHECK-NEXT: vpshufd $3, %ymm0, %ymm2 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0x70,0xd0,0x03]
; CHECK-NEXT: ## ymm2 = k1[3,0,0,0,7,4,4,4]
-; CHECK-NEXT: vpshufd $3, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x70,0xc0,0x03]
+; CHECK-NEXT: vpshufd $3, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0x70,0xc0,0x03]
; CHECK-NEXT: ## ymm0 = ymm0[3,0,0,0,7,4,4,4]
; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1 ## encoding: [0x62,0xf1,0x75,0x28,0xfe,0xca]
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ## encoding: [0x62,0xf1,0x75,0x28,0xfe,0xc0]
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