[PATCH] D20931: [X86] Reduce the width of multiplification when its operands are extended from i8 or i16

[Eli Friedman via llvm-commits]

eli.friedman added a subscriber: eli.friedman.
eli.friedman added a comment.

The testcases are a bit more complicated than they need to be; could you reduce them to just the minimal IR? In particular, including the loops makes it harder to read.

Also, missing testcase for the multiply-by-constant case.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:26450
@@ +26449,3 @@
+/// For pattern1, mul <N x i32> can be shrinked to mul <N x i16>.
+/// For pattern2, mul <N x i32> can be shrinked to mul <N x i16>
+/// plus mulhs/mulhw <N x i16>.
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"shrunk", not "shrinked"... but you might want to use "narrowed" here instead.

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Comment at: lib/Target/X86/X86ISelLowering.cpp:26477
@@ +26476,3 @@
+      N0.getOpcode() == ISD::SIGN_EXTEND) {
+    IsSigned = (N0.getOpcode() == ISD::SIGN_EXTEND) ? true : false;
+    if (N0.getOperand(0).getValueType().getVectorElementType() == MVT::i8)
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What if one side is signed, and the other is unsigned?

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Comment at: lib/Target/X86/X86ISelLowering.cpp:26493
@@ +26492,3 @@
+      N1Size = SIZEI16;
+  }
+
----------------
Repeated code; should be refactored.

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Comment at: lib/Target/X86/X86ISelLowering.cpp:26507
@@ +26506,3 @@
+      N1Size = SIZEI16;
+  }
+
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This is not what you want.  The constant vector is "zero-extended" if ZEXT(TRUNC(vec))==vec, and "sign-extended" if SEXT(TRUNC(vec)) == vec.  Computing whether the vector is a splat has no relation to either of those properties.

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Comment at: lib/Target/X86/X86ISelLowering.cpp:26612
@@ +26611,3 @@
+    }
+  }
+}
----------------
There's massive code duplication here; needs to be refactored.  Maybe make splitting the inputs if necessary and actually computing the product separate steps?


Repository:
  rL LLVM

http://reviews.llvm.org/D20931