[llvm] r271516 - [X86][SSE] Added non-temporal load tests for vector types
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 2 06:51:51 PDT 2016
Author: rksimon
Date: Thu Jun 2 08:51:50 2016
New Revision: 271516
URL: http://llvm.org/viewvc/llvm-project?rev=271516&view=rev
Log:
[X86][SSE] Added non-temporal load tests for vector types
These currently lower to regular loads instead of MOVNTDQA
Modified:
llvm/trunk/test/CodeGen/X86/fast-isel-nontemporal.ll
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-nontemporal.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-nontemporal.ll?rev=271516&r1=271515&r2=271516&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-nontemporal.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-nontemporal.ll Thu Jun 2 08:51:50 2016
@@ -204,6 +204,130 @@ entry:
}
;
+; 128-bit Vector Loads
+;
+
+define <4 x float> @test_load_nt4xfloat(<4 x float>* nocapture %ptr) {
+; SSE-LABEL: test_load_nt4xfloat:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: movaps (%rdi), %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_load_nt4xfloat:
+; AVX: # BB#0: # %entry
+; AVX-NEXT: vmovaps (%rdi), %xmm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_load_nt4xfloat:
+; AVX512: # BB#0: # %entry
+; AVX512-NEXT: vmovaps (%rdi), %xmm0
+; AVX512-NEXT: retq
+entry:
+ %0 = load <4 x float>, <4 x float>* %ptr, align 16, !nontemporal !1
+ ret <4 x float> %0
+}
+
+define <2 x double> @test_load_nt2xdouble(<2 x double>* nocapture %ptr) {
+; SSE-LABEL: test_load_nt2xdouble:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: movapd (%rdi), %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_load_nt2xdouble:
+; AVX: # BB#0: # %entry
+; AVX-NEXT: vmovapd (%rdi), %xmm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_load_nt2xdouble:
+; AVX512: # BB#0: # %entry
+; AVX512-NEXT: vmovapd (%rdi), %xmm0
+; AVX512-NEXT: retq
+entry:
+ %0 = load <2 x double>, <2 x double>* %ptr, align 16, !nontemporal !1
+ ret <2 x double> %0
+}
+
+define <16 x i8> @test_load_nt16xi8(<16 x i8>* nocapture %ptr) {
+; SSE-LABEL: test_load_nt16xi8:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: movdqa (%rdi), %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_load_nt16xi8:
+; AVX: # BB#0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %xmm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_load_nt16xi8:
+; AVX512: # BB#0: # %entry
+; AVX512-NEXT: vmovdqa (%rdi), %xmm0
+; AVX512-NEXT: retq
+entry:
+ %0 = load <16 x i8>, <16 x i8>* %ptr, align 16, !nontemporal !1
+ ret <16 x i8> %0
+}
+
+define <8 x i16> @test_load_nt8xi16(<8 x i16>* nocapture %ptr) {
+; SSE-LABEL: test_load_nt8xi16:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: movdqa (%rdi), %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_load_nt8xi16:
+; AVX: # BB#0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %xmm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_load_nt8xi16:
+; AVX512: # BB#0: # %entry
+; AVX512-NEXT: vmovdqa (%rdi), %xmm0
+; AVX512-NEXT: retq
+entry:
+ %0 = load <8 x i16>, <8 x i16>* %ptr, align 16, !nontemporal !1
+ ret <8 x i16> %0
+}
+
+define <4 x i32> @test_load_nt4xi32(<4 x i32>* nocapture %ptr) {
+; SSE-LABEL: test_load_nt4xi32:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: movdqa (%rdi), %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_load_nt4xi32:
+; AVX: # BB#0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %xmm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_load_nt4xi32:
+; AVX512: # BB#0: # %entry
+; AVX512-NEXT: vmovdqa (%rdi), %xmm0
+; AVX512-NEXT: retq
+entry:
+ %0 = load <4 x i32>, <4 x i32>* %ptr, align 16, !nontemporal !1
+ ret <4 x i32> %0
+}
+
+define <2 x i64> @test_load_nt2xi64(<2 x i64>* nocapture %ptr) {
+; SSE-LABEL: test_load_nt2xi64:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: movdqa (%rdi), %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_load_nt2xi64:
+; AVX: # BB#0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %xmm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_load_nt2xi64:
+; AVX512: # BB#0: # %entry
+; AVX512-NEXT: vmovdqa (%rdi), %xmm0
+; AVX512-NEXT: retq
+entry:
+ %0 = load <2 x i64>, <2 x i64>* %ptr, align 16, !nontemporal !1
+ ret <2 x i64> %0
+}
+
+;
; 256-bit Vector Stores
;
@@ -340,6 +464,136 @@ entry:
}
;
+; 256-bit Vector Loads
+;
+
+define <8 x float> @test_load_nt8xfloat(<8 x float>* nocapture %ptr) {
+; SSE-LABEL: test_load_nt8xfloat:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: movaps (%rdi), %xmm0
+; SSE-NEXT: movaps 16(%rdi), %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_load_nt8xfloat:
+; AVX: # BB#0: # %entry
+; AVX-NEXT: vmovaps (%rdi), %ymm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_load_nt8xfloat:
+; AVX512: # BB#0: # %entry
+; AVX512-NEXT: vmovaps (%rdi), %ymm0
+; AVX512-NEXT: retq
+entry:
+ %0 = load <8 x float>, <8 x float>* %ptr, align 32, !nontemporal !1
+ ret <8 x float> %0
+}
+
+define <4 x double> @test_load_nt4xdouble(<4 x double>* nocapture %ptr) {
+; SSE-LABEL: test_load_nt4xdouble:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: movapd (%rdi), %xmm0
+; SSE-NEXT: movapd 16(%rdi), %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_load_nt4xdouble:
+; AVX: # BB#0: # %entry
+; AVX-NEXT: vmovapd (%rdi), %ymm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_load_nt4xdouble:
+; AVX512: # BB#0: # %entry
+; AVX512-NEXT: vmovapd (%rdi), %ymm0
+; AVX512-NEXT: retq
+entry:
+ %0 = load <4 x double>, <4 x double>* %ptr, align 32, !nontemporal !1
+ ret <4 x double> %0
+}
+
+define <32 x i8> @test_load_nt32xi8(<32 x i8>* nocapture %ptr) {
+; SSE-LABEL: test_load_nt32xi8:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: movaps (%rdi), %xmm0
+; SSE-NEXT: movaps 16(%rdi), %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_load_nt32xi8:
+; AVX: # BB#0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %ymm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_load_nt32xi8:
+; AVX512: # BB#0: # %entry
+; AVX512-NEXT: vmovdqa (%rdi), %ymm0
+; AVX512-NEXT: retq
+entry:
+ %0 = load <32 x i8>, <32 x i8>* %ptr, align 32, !nontemporal !1
+ ret <32 x i8> %0
+}
+
+define <16 x i16> @test_load_nt16xi16(<16 x i16>* nocapture %ptr) {
+; SSE-LABEL: test_load_nt16xi16:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: movaps (%rdi), %xmm0
+; SSE-NEXT: movaps 16(%rdi), %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_load_nt16xi16:
+; AVX: # BB#0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %ymm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_load_nt16xi16:
+; AVX512: # BB#0: # %entry
+; AVX512-NEXT: vmovdqa (%rdi), %ymm0
+; AVX512-NEXT: retq
+entry:
+ %0 = load <16 x i16>, <16 x i16>* %ptr, align 32, !nontemporal !1
+ ret <16 x i16> %0
+}
+
+define <8 x i32> @test_load_nt8xi32(<8 x i32>* nocapture %ptr) {
+; SSE-LABEL: test_load_nt8xi32:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: movaps (%rdi), %xmm0
+; SSE-NEXT: movaps 16(%rdi), %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_load_nt8xi32:
+; AVX: # BB#0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %ymm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_load_nt8xi32:
+; AVX512: # BB#0: # %entry
+; AVX512-NEXT: vmovdqa (%rdi), %ymm0
+; AVX512-NEXT: retq
+entry:
+ %0 = load <8 x i32>, <8 x i32>* %ptr, align 32, !nontemporal !1
+ ret <8 x i32> %0
+}
+
+define <4 x i64> @test_load_nt4xi64(<4 x i64>* nocapture %ptr) {
+; SSE-LABEL: test_load_nt4xi64:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: movaps (%rdi), %xmm0
+; SSE-NEXT: movaps 16(%rdi), %xmm1
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_load_nt4xi64:
+; AVX: # BB#0: # %entry
+; AVX-NEXT: vmovdqa (%rdi), %ymm0
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_load_nt4xi64:
+; AVX512: # BB#0: # %entry
+; AVX512-NEXT: vmovdqa (%rdi), %ymm0
+; AVX512-NEXT: retq
+entry:
+ %0 = load <4 x i64>, <4 x i64>* %ptr, align 32, !nontemporal !1
+ ret <4 x i64> %0
+}
+
+;
; 512-bit Vector Stores
;
@@ -505,4 +759,58 @@ entry:
ret void
}
+;
+; 512-bit Vector Loads
+;
+
+define <16 x float> @test_load_nt16xfloat(<16 x float>* nocapture %ptr) {
+; SSE-LABEL: test_load_nt16xfloat:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: movaps (%rdi), %xmm0
+; SSE-NEXT: movaps 16(%rdi), %xmm1
+; SSE-NEXT: movaps 32(%rdi), %xmm2
+; SSE-NEXT: movaps 48(%rdi), %xmm3
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_load_nt16xfloat:
+; AVX: # BB#0: # %entry
+; AVX-NEXT: vmovaps (%rdi), %ymm0
+; AVX-NEXT: vmovaps 32(%rdi), %ymm1
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_load_nt16xfloat:
+; AVX512: # BB#0: # %entry
+; AVX512-NEXT: vmovaps (%rdi), %zmm0
+; AVX512-NEXT: retq
+entry:
+ %0 = load <16 x float>, <16 x float>* %ptr, align 64, !nontemporal !1
+ ret <16 x float> %0
+}
+
+define <8 x double> @test_load_nt8xdouble(<8 x double>* nocapture %ptr) {
+; SSE-LABEL: test_load_nt8xdouble:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: movapd (%rdi), %xmm0
+; SSE-NEXT: movapd 16(%rdi), %xmm1
+; SSE-NEXT: movapd 32(%rdi), %xmm2
+; SSE-NEXT: movapd 48(%rdi), %xmm3
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_load_nt8xdouble:
+; AVX: # BB#0: # %entry
+; AVX-NEXT: vmovapd (%rdi), %ymm0
+; AVX-NEXT: vmovapd 32(%rdi), %ymm1
+; AVX-NEXT: retq
+;
+; AVX512-LABEL: test_load_nt8xdouble:
+; AVX512: # BB#0: # %entry
+; AVX512-NEXT: vmovapd (%rdi), %zmm0
+; AVX512-NEXT: retq
+entry:
+ %0 = load <8 x double>, <8 x double>* %ptr, align 64, !nontemporal !1
+ ret <8 x double> %0
+}
+
+; TODO - 512-bit integer vector loads
+
!1 = !{i32 1}
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