[PATCH] D20897: [AVX512/AVX][Intrinsics] Fix Variable Bit Shift Right Arithmetic intrinsic lowering.

[Igor Breger via llvm-commits]

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[AVX512/AVX][Intrinsics] Fix Variable Bit Shift Right Arithmetic intrinsic lowering.
Intel SRA intrinsic behavior are different from LLVM ashr instruction.
LLVM ashr instruction : If op2 is (statically or dynamically) equal to or larger than the number of bits in op1, the result is undefined.
Intel SRA: If the unsigned integer value specified in the respective data element of the second source operand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination data element are filled with the corresponding sign bit of the source element.

Perform constant folding before SRA creation to match intrinsic behavior.

Repository:
  rL LLVM

http://reviews.llvm.org/D20897

Files:
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86IntrinsicsInfo.h
  test/CodeGen/X86/avx2-intrinsics-x86.ll
  test/CodeGen/X86/avx512bw-intrinsics.ll
  test/CodeGen/X86/avx512vl-intrinsics.ll

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