[llvm] r271341 - [X86]: Add a pattern that uses GR16_ABCD rather than GR32_ABCD to avoid falsely marking whole 32 bit register as live.

[Kevin B. Smith via llvm-commits]

Author: kbsmith1
Date: Tue May 31 17:00:12 2016
New Revision: 271341

URL: http://llvm.org/viewvc/llvm-project?rev=271341&view=rev
Log:
[X86]: Add a pattern that uses GR16_ABCD rather than GR32_ABCD to avoid falsely marking whole 32 bit register as live.
Differential Revision: http://reviews.llvm.org/D20649

Added:
    llvm/trunk/test/CodeGen/X86/i16lshr8pat.ll
Modified:
    llvm/trunk/lib/Target/X86/X86InstrCompiler.td

Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=271341&r1=271340&r2=271341&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Tue May 31 17:00:12 2016
@@ -1550,6 +1550,10 @@ def : Pat<(i8 (trunc (srl_su GR16:$src,
           (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
                           sub_8bit_hi)>,
       Requires<[Not64BitMode]>;
+def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))),
+          (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
+                          sub_8bit_hi)>,
+      Requires<[Not64BitMode]>;
 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
           (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
                           sub_8bit_hi)>,

Added: llvm/trunk/test/CodeGen/X86/i16lshr8pat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/i16lshr8pat.ll?rev=271341&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/i16lshr8pat.ll (added)
+++ llvm/trunk/test/CodeGen/X86/i16lshr8pat.ll Tue May 31 17:00:12 2016
@@ -0,0 +1,32 @@
+; RUN: llc -march=x86 -stop-after expand-isel-pseudos <%s 2>&1 | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
+target triple = "i386-unknown-linux-gnu"
+
+; This test checks to make sure the lshr in %then1 block gets expanded using
+; GR16_ABCD pattern rather than GR32_ABCD pattern.  By using the 16-bit pattern
+; this doesn't make the register liveness information look like the whole
+; 32-bit register is a live value, and allows generally better live register
+; analysis.
+; CHECK-LABEL: bb.1.then1:
+; CHECK-NOT:   IMPLICIT_DEF
+; CHECK-NOT:   INSERT_SUBREG
+; CHECK:       sub_8bit_hi
+; CHECK-LABEL: bb.2.endif1:
+
+define i16 @foo4(i32 %prec, i8 *%dst, i16 *%src) {
+entry:
+  %cnd = icmp ne i32 %prec, 0
+  %t0 = load i16, i16 *%src, align 2
+  br i1 %cnd, label %then1, label %endif1
+
+then1:
+  %shr = lshr i16 %t0, 8
+  %conv = trunc i16 %shr to i8
+  store i8 %conv, i8 *%dst, align 1
+  br label %endif1
+
+endif1:
+  %t2 = phi i16 [0, %then1], [%t0, %entry]
+  ret i16 %t2
+}