[llvm] r271281 - [Hexagon] Disable expanding MUX instructions that define a subregister

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Tue May 31 09:27:10 2016
New Revision: 271281

URL: http://llvm.org/viewvc/llvm-project?rev=271281&view=rev
Log:
[Hexagon] Disable expanding MUX instructions that define a subregister

The code in HexagonExpandCondsets.cpp does not handle those cases at the
moment.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp?rev=271281&r1=271280&r2=271281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp Tue May 31 09:27:10 2016
@@ -991,6 +991,11 @@ bool HexagonExpandCondsets::predicate(Ma
   // some registers, which would complicate the transformation considerably.
   if (!MS.isKill())
     return false;
+  // Avoid predicating instructions that define a subregister. The code
+  // does not handle correctly cases where both subregisters of a register
+  // are defined by a condset.
+  if (MD.getSubReg())
+    return false;
 
   RegisterRef RT(MS);
   unsigned PredR = MP.getReg();