[llvm] r271226 - [X86][SSE] Renamed pmovxrm tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon May 30 12:15:44 PDT 2016
Author: rksimon
Date: Mon May 30 14:14:37 2016
New Revision: 271226
URL: http://llvm.org/viewvc/llvm-project?rev=271226&view=rev
Log:
[X86][SSE] Renamed pmovxrm tests
These aren't intrinsics anymore - as discussed on D20686
Added:
llvm/trunk/test/CodeGen/X86/avx2-pmovxrm.ll
- copied unchanged from r271225, llvm/trunk/test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll
llvm/trunk/test/CodeGen/X86/sse41-pmovxrm.ll
- copied unchanged from r271225, llvm/trunk/test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll
Removed:
llvm/trunk/test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll
llvm/trunk/test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll
Removed: llvm/trunk/test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll?rev=271225&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll (removed)
@@ -1,201 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=X32
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=X64
-
-define <16 x i16> @test_llvm_x86_avx2_pmovsxbw(<16 x i8>* %a) {
-; X32-LABEL: test_llvm_x86_avx2_pmovsxbw:
-; X32: ## BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmovsxbw (%eax), %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_llvm_x86_avx2_pmovsxbw:
-; X64: ## BB#0:
-; X64-NEXT: vpmovsxbw (%rdi), %ymm0
-; X64-NEXT: retq
- %1 = load <16 x i8>, <16 x i8>* %a, align 1
- %2 = sext <16 x i8> %1 to <16 x i16>
- ret <16 x i16> %2
-}
-
-define <8 x i32> @test_llvm_x86_avx2_pmovsxbd(<16 x i8>* %a) {
-; X32-LABEL: test_llvm_x86_avx2_pmovsxbd:
-; X32: ## BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmovsxbd (%eax), %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_llvm_x86_avx2_pmovsxbd:
-; X64: ## BB#0:
-; X64-NEXT: vpmovsxbd (%rdi), %ymm0
-; X64-NEXT: retq
- %1 = load <16 x i8>, <16 x i8>* %a, align 1
- %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- %3 = sext <8 x i8> %2 to <8 x i32>
- ret <8 x i32> %3
-}
-
-define <4 x i64> @test_llvm_x86_avx2_pmovsxbq(<16 x i8>* %a) {
-; X32-LABEL: test_llvm_x86_avx2_pmovsxbq:
-; X32: ## BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmovsxbq (%eax), %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_llvm_x86_avx2_pmovsxbq:
-; X64: ## BB#0:
-; X64-NEXT: vpmovsxbq (%rdi), %ymm0
-; X64-NEXT: retq
- %1 = load <16 x i8>, <16 x i8>* %a, align 1
- %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- %3 = sext <4 x i8> %2 to <4 x i64>
- ret <4 x i64> %3
-}
-
-define <8 x i32> @test_llvm_x86_avx2_pmovsxwd(<8 x i16>* %a) {
-; X32-LABEL: test_llvm_x86_avx2_pmovsxwd:
-; X32: ## BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmovsxwd (%eax), %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_llvm_x86_avx2_pmovsxwd:
-; X64: ## BB#0:
-; X64-NEXT: vpmovsxwd (%rdi), %ymm0
-; X64-NEXT: retq
- %1 = load <8 x i16>, <8 x i16>* %a, align 1
- %2 = sext <8 x i16> %1 to <8 x i32>
- ret <8 x i32> %2
-}
-
-define <4 x i64> @test_llvm_x86_avx2_pmovsxwq(<8 x i16>* %a) {
-; X32-LABEL: test_llvm_x86_avx2_pmovsxwq:
-; X32: ## BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmovsxwq (%eax), %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_llvm_x86_avx2_pmovsxwq:
-; X64: ## BB#0:
-; X64-NEXT: vpmovsxwq (%rdi), %ymm0
-; X64-NEXT: retq
- %1 = load <8 x i16>, <8 x i16>* %a, align 1
- %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- %3 = sext <4 x i16> %2 to <4 x i64>
- ret <4 x i64> %3
-}
-
-define <4 x i64> @test_llvm_x86_avx2_pmovsxdq(<4 x i32>* %a) {
-; X32-LABEL: test_llvm_x86_avx2_pmovsxdq:
-; X32: ## BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmovsxdq (%eax), %ymm0
-; X32-NEXT: retl
-;
-; X64-LABEL: test_llvm_x86_avx2_pmovsxdq:
-; X64: ## BB#0:
-; X64-NEXT: vpmovsxdq (%rdi), %ymm0
-; X64-NEXT: retq
- %1 = load <4 x i32>, <4 x i32>* %a, align 1
- %2 = sext <4 x i32> %1 to <4 x i64>
- ret <4 x i64> %2
-}
-
-define <16 x i16> @test_llvm_x86_avx2_pmovzxbw(<16 x i8>* %a) {
-; X32-LABEL: test_llvm_x86_avx2_pmovzxbw:
-; X32: ## BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmovzxbw {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_llvm_x86_avx2_pmovzxbw:
-; X64: ## BB#0:
-; X64-NEXT: vpmovzxbw {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero
-; X64-NEXT: retq
- %1 = load <16 x i8>, <16 x i8>* %a, align 1
- %2 = zext <16 x i8> %1 to <16 x i16>
- ret <16 x i16> %2
-}
-
-define <8 x i32> @test_llvm_x86_avx2_pmovzxbd(<16 x i8>* %a) {
-; X32-LABEL: test_llvm_x86_avx2_pmovzxbd:
-; X32: ## BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmovzxbd {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_llvm_x86_avx2_pmovzxbd:
-; X64: ## BB#0:
-; X64-NEXT: vpmovzxbd {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
-; X64-NEXT: retq
- %1 = load <16 x i8>, <16 x i8>* %a, align 1
- %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- %3 = zext <8 x i8> %2 to <8 x i32>
- ret <8 x i32> %3
-}
-
-define <4 x i64> @test_llvm_x86_avx2_pmovzxbq(<16 x i8>* %a) {
-; X32-LABEL: test_llvm_x86_avx2_pmovzxbq:
-; X32: ## BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmovzxbq {{.*#+}} ymm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero,mem[2],zero,zero,zero,zero,zero,zero,zero,mem[3],zero,zero,zero,zero,zero,zero,zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_llvm_x86_avx2_pmovzxbq:
-; X64: ## BB#0:
-; X64-NEXT: vpmovzxbq {{.*#+}} ymm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero,mem[2],zero,zero,zero,zero,zero,zero,zero,mem[3],zero,zero,zero,zero,zero,zero,zero
-; X64-NEXT: retq
- %1 = load <16 x i8>, <16 x i8>* %a, align 1
- %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- %3 = zext <4 x i8> %2 to <4 x i64>
- ret <4 x i64> %3
-}
-
-define <8 x i32> @test_llvm_x86_avx2_pmovzxwd(<8 x i16>* %a) {
-; X32-LABEL: test_llvm_x86_avx2_pmovzxwd:
-; X32: ## BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_llvm_x86_avx2_pmovzxwd:
-; X64: ## BB#0:
-; X64-NEXT: vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
-; X64-NEXT: retq
- %1 = load <8 x i16>, <8 x i16>* %a, align 1
- %2 = zext <8 x i16> %1 to <8 x i32>
- ret <8 x i32> %2
-}
-
-define <4 x i64> @test_llvm_x86_avx2_pmovzxwq(<8 x i16>* %a) {
-; X32-LABEL: test_llvm_x86_avx2_pmovzxwq:
-; X32: ## BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmovzxwq {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_llvm_x86_avx2_pmovzxwq:
-; X64: ## BB#0:
-; X64-NEXT: vpmovzxwq {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
-; X64-NEXT: retq
- %1 = load <8 x i16>, <8 x i16>* %a, align 1
- %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- %3 = zext <4 x i16> %2 to <4 x i64>
- ret <4 x i64> %3
-}
-
-define <4 x i64> @test_llvm_x86_avx2_pmovzxdq(<4 x i32>* %a) {
-; X32-LABEL: test_llvm_x86_avx2_pmovzxdq:
-; X32: ## BB#0:
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: vpmovzxdq {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
-; X32-NEXT: retl
-;
-; X64-LABEL: test_llvm_x86_avx2_pmovzxdq:
-; X64: ## BB#0:
-; X64-NEXT: vpmovzxdq {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
-; X64-NEXT: retq
- %1 = load <4 x i32>, <4 x i32>* %a, align 1
- %2 = zext <4 x i32> %1 to <4 x i64>
- ret <4 x i64> %2
-}
Removed: llvm/trunk/test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll?rev=271225&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll (removed)
@@ -1,195 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
-
-define <8 x i16> @test_llvm_x86_sse41_pmovsxbw(<16 x i8>* %a) {
-; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbw:
-; SSE41: ## BB#0:
-; SSE41-NEXT: pmovsxbw (%rdi), %xmm0
-; SSE41-NEXT: retq
-;
-; AVX-LABEL: test_llvm_x86_sse41_pmovsxbw:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovsxbw (%rdi), %xmm0
-; AVX-NEXT: retq
- %1 = load <16 x i8>, <16 x i8>* %a, align 1
- %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- %3 = sext <8 x i8> %2 to <8 x i16>
- ret <8 x i16> %3
-}
-
-define <4 x i32> @test_llvm_x86_sse41_pmovsxbd(<16 x i8>* %a) {
-; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbd:
-; SSE41: ## BB#0:
-; SSE41-NEXT: pmovsxbd (%rdi), %xmm0
-; SSE41-NEXT: retq
-;
-; AVX-LABEL: test_llvm_x86_sse41_pmovsxbd:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovsxbd (%rdi), %xmm0
-; AVX-NEXT: retq
- %1 = load <16 x i8>, <16 x i8>* %a, align 1
- %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- %3 = sext <4 x i8> %2 to <4 x i32>
- ret <4 x i32> %3
-}
-
-define <2 x i64> @test_llvm_x86_sse41_pmovsxbq(<16 x i8>* %a) {
-; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbq:
-; SSE41: ## BB#0:
-; SSE41-NEXT: pmovsxbq (%rdi), %xmm0
-; SSE41-NEXT: retq
-;
-; AVX-LABEL: test_llvm_x86_sse41_pmovsxbq:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovsxbq (%rdi), %xmm0
-; AVX-NEXT: retq
- %1 = load <16 x i8>, <16 x i8>* %a, align 1
- %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
- %3 = sext <2 x i8> %2 to <2 x i64>
- ret <2 x i64> %3
-}
-
-define <4 x i32> @test_llvm_x86_sse41_pmovsxwd(<8 x i16>* %a) {
-; SSE41-LABEL: test_llvm_x86_sse41_pmovsxwd:
-; SSE41: ## BB#0:
-; SSE41-NEXT: pmovsxwd (%rdi), %xmm0
-; SSE41-NEXT: retq
-;
-; AVX-LABEL: test_llvm_x86_sse41_pmovsxwd:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovsxwd (%rdi), %xmm0
-; AVX-NEXT: retq
- %1 = load <8 x i16>, <8 x i16>* %a, align 1
- %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- %3 = sext <4 x i16> %2 to <4 x i32>
- ret <4 x i32> %3
-}
-
-define <2 x i64> @test_llvm_x86_sse41_pmovsxwq(<8 x i16>* %a) {
-; SSE41-LABEL: test_llvm_x86_sse41_pmovsxwq:
-; SSE41: ## BB#0:
-; SSE41-NEXT: pmovsxwq (%rdi), %xmm0
-; SSE41-NEXT: retq
-;
-; AVX-LABEL: test_llvm_x86_sse41_pmovsxwq:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovsxwq (%rdi), %xmm0
-; AVX-NEXT: retq
- %1 = load <8 x i16>, <8 x i16>* %a, align 1
- %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
- %3 = sext <2 x i16> %2 to <2 x i64>
- ret <2 x i64> %3
-}
-
-define <2 x i64> @test_llvm_x86_sse41_pmovsxdq(<4 x i32>* %a) {
-; SSE41-LABEL: test_llvm_x86_sse41_pmovsxdq:
-; SSE41: ## BB#0:
-; SSE41-NEXT: pmovsxdq (%rdi), %xmm0
-; SSE41-NEXT: retq
-;
-; AVX-LABEL: test_llvm_x86_sse41_pmovsxdq:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovsxdq (%rdi), %xmm0
-; AVX-NEXT: retq
- %1 = load <4 x i32>, <4 x i32>* %a, align 1
- %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
- %3 = sext <2 x i32> %2 to <2 x i64>
- ret <2 x i64> %3
-}
-
-define <8 x i16> @test_llvm_x86_sse41_pmovzxbw(<16 x i8>* %a) {
-; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbw:
-; SSE41: ## BB#0:
-; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
-; SSE41-NEXT: retq
-;
-; AVX-LABEL: test_llvm_x86_sse41_pmovzxbw:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
-; AVX-NEXT: retq
- %1 = load <16 x i8>, <16 x i8>* %a, align 1
- %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- %3 = zext <8 x i8> %2 to <8 x i16>
- ret <8 x i16> %3
-}
-
-define <4 x i32> @test_llvm_x86_sse41_pmovzxbd(<16 x i8>* %a) {
-; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbd:
-; SSE41: ## BB#0:
-; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
-; SSE41-NEXT: retq
-;
-; AVX-LABEL: test_llvm_x86_sse41_pmovzxbd:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
-; AVX-NEXT: retq
- %1 = load <16 x i8>, <16 x i8>* %a, align 1
- %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- %3 = zext <4 x i8> %2 to <4 x i32>
- ret <4 x i32> %3
-}
-
-define <2 x i64> @test_llvm_x86_sse41_pmovzxbq(<16 x i8>* %a) {
-; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbq:
-; SSE41: ## BB#0:
-; SSE41-NEXT: pmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
-; SSE41-NEXT: retq
-;
-; AVX-LABEL: test_llvm_x86_sse41_pmovzxbq:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
-; AVX-NEXT: retq
- %1 = load <16 x i8>, <16 x i8>* %a, align 1
- %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
- %3 = zext <2 x i8> %2 to <2 x i64>
- ret <2 x i64> %3
-}
-
-define <4 x i32> @test_llvm_x86_sse41_pmovzxwd(<8 x i16>* %a) {
-; SSE41-LABEL: test_llvm_x86_sse41_pmovzxwd:
-; SSE41: ## BB#0:
-; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
-; SSE41-NEXT: retq
-;
-; AVX-LABEL: test_llvm_x86_sse41_pmovzxwd:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
-; AVX-NEXT: retq
- %1 = load <8 x i16>, <8 x i16>* %a, align 1
- %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- %3 = zext <4 x i16> %2 to <4 x i32>
- ret <4 x i32> %3
-}
-
-define <2 x i64> @test_llvm_x86_sse41_pmovzxwq(<8 x i16>* %a) {
-; SSE41-LABEL: test_llvm_x86_sse41_pmovzxwq:
-; SSE41: ## BB#0:
-; SSE41-NEXT: pmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
-; SSE41-NEXT: retq
-;
-; AVX-LABEL: test_llvm_x86_sse41_pmovzxwq:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
-; AVX-NEXT: retq
- %1 = load <8 x i16>, <8 x i16>* %a, align 1
- %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
- %3 = zext <2 x i16> %2 to <2 x i64>
- ret <2 x i64> %3
-}
-
-define <2 x i64> @test_llvm_x86_sse41_pmovzxdq(<4 x i32>* %a) {
-; SSE41-LABEL: test_llvm_x86_sse41_pmovzxdq:
-; SSE41: ## BB#0:
-; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
-; SSE41-NEXT: retq
-;
-; AVX-LABEL: test_llvm_x86_sse41_pmovzxdq:
-; AVX: ## BB#0:
-; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
-; AVX-NEXT: retq
- %1 = load <4 x i32>, <4 x i32>* %a, align 1
- %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
- %3 = zext <2 x i32> %2 to <2 x i64>
- ret <2 x i64> %3
-}
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