[llvm] r271174 - [X86] Simplify some of the autoupgrade code. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat May 28 23:37:34 PDT 2016
Author: ctopper
Date: Sun May 29 01:37:33 2016
New Revision: 271174
URL: http://llvm.org/viewvc/llvm-project?rev=271174&view=rev
Log:
[X86] Simplify some of the autoupgrade code. NFC
Modified:
llvm/trunk/lib/IR/AutoUpgrade.cpp
Modified: llvm/trunk/lib/IR/AutoUpgrade.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/AutoUpgrade.cpp?rev=271174&r1=271173&r2=271174&view=diff
==============================================================================
--- llvm/trunk/lib/IR/AutoUpgrade.cpp (original)
+++ llvm/trunk/lib/IR/AutoUpgrade.cpp Sun May 29 01:37:33 2016
@@ -304,75 +304,70 @@ bool llvm::UpgradeGlobalVariable(GlobalV
// Handles upgrading SSE2 and AVX2 PSLLDQ intrinsics by converting them
// to byte shuffles.
static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, LLVMContext &C,
- Value *Op, unsigned NumLanes,
- unsigned Shift) {
- // Each lane is 16 bytes.
- unsigned NumElts = NumLanes * 16;
+ Value *Op, unsigned Shift) {
+ Type *ResultTy = Op->getType();
+ unsigned NumElts = ResultTy->getVectorNumElements() * 8;
// Bitcast from a 64-bit element type to a byte element type.
- Op = Builder.CreateBitCast(Op,
- VectorType::get(Type::getInt8Ty(C), NumElts),
- "cast");
+ Type *VecTy = VectorType::get(Type::getInt8Ty(C), NumElts);
+ Op = Builder.CreateBitCast(Op, VecTy, "cast");
+
// We'll be shuffling in zeroes.
- Value *Res = ConstantVector::getSplat(NumElts, Builder.getInt8(0));
+ Value *Res = Constant::getNullValue(VecTy);
// If shift is less than 16, emit a shuffle to move the bytes. Otherwise,
// we'll just return the zero vector.
if (Shift < 16) {
- SmallVector<Constant*, 32> Idxs;
+ int Idxs[32];
// 256-bit version is split into two 16-byte lanes.
for (unsigned l = 0; l != NumElts; l += 16)
for (unsigned i = 0; i != 16; ++i) {
unsigned Idx = NumElts + i - Shift;
if (Idx < NumElts)
Idx -= NumElts - 16; // end of lane, switch operand.
- Idxs.push_back(Builder.getInt32(Idx + l));
+ Idxs[l + i] = Idx + l;
}
- Res = Builder.CreateShuffleVector(Res, Op, ConstantVector::get(Idxs));
+ Res = Builder.CreateShuffleVector(Res, Op, makeArrayRef(Idxs, NumElts));
}
// Bitcast back to a 64-bit element type.
- return Builder.CreateBitCast(Res,
- VectorType::get(Type::getInt64Ty(C), 2*NumLanes),
- "cast");
+ return Builder.CreateBitCast(Res, ResultTy, "cast");
}
// Handles upgrading SSE2 and AVX2 PSRLDQ intrinsics by converting them
// to byte shuffles.
static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, LLVMContext &C,
- Value *Op, unsigned NumLanes,
+ Value *Op,
unsigned Shift) {
- // Each lane is 16 bytes.
- unsigned NumElts = NumLanes * 16;
+ Type *ResultTy = Op->getType();
+ unsigned NumElts = ResultTy->getVectorNumElements() * 8;
// Bitcast from a 64-bit element type to a byte element type.
- Op = Builder.CreateBitCast(Op,
- VectorType::get(Type::getInt8Ty(C), NumElts),
- "cast");
+ Type *VecTy = VectorType::get(Type::getInt8Ty(C), NumElts);
+ Op = Builder.CreateBitCast(Op, VecTy, "cast");
+
// We'll be shuffling in zeroes.
- Value *Res = ConstantVector::getSplat(NumElts, Builder.getInt8(0));
+ Value *Res = Constant::getNullValue(VecTy);
// If shift is less than 16, emit a shuffle to move the bytes. Otherwise,
// we'll just return the zero vector.
if (Shift < 16) {
- SmallVector<Constant*, 32> Idxs;
+ int Idxs[32];
// 256-bit version is split into two 16-byte lanes.
for (unsigned l = 0; l != NumElts; l += 16)
for (unsigned i = 0; i != 16; ++i) {
unsigned Idx = i + Shift;
if (Idx >= 16)
Idx += NumElts - 16; // end of lane, switch operand.
- Idxs.push_back(Builder.getInt32(Idx + l));
+ Idxs[l + i] = Idx + l;
}
- Res = Builder.CreateShuffleVector(Op, Res, ConstantVector::get(Idxs));
+ Res = Builder.CreateShuffleVector(Op, Res, makeArrayRef(Idxs, NumElts));
}
// Bitcast back to a 64-bit element type.
- return Builder.CreateBitCast(Res,
- VectorType::get(Type::getInt64Ty(C), 2*NumLanes),
- "cast");
+ return Builder.CreateBitCast(Res, ResultTy, "cast");
}
// UpgradeIntrinsicCall - Upgrade a call to an old intrinsic to be a call the
@@ -583,46 +578,28 @@ void llvm::UpgradeIntrinsicCall(CallInst
Type *MaskTy = VectorType::get(Type::getInt32Ty(C), NumElts);
Rep = Builder.CreateShuffleVector(Op, UndefValue::get(Op->getType()),
Constant::getNullValue(MaskTy));
- } else if (Name == "llvm.x86.sse2.psll.dq") {
- // 128-bit shift left specified in bits.
- unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
- Rep = UpgradeX86PSLLDQIntrinsics(Builder, C, CI->getArgOperand(0), 1,
- Shift / 8); // Shift is in bits.
- } else if (Name == "llvm.x86.sse2.psrl.dq") {
- // 128-bit shift right specified in bits.
+ } else if (Name == "llvm.x86.sse2.psll.dq" ||
+ Name == "llvm.x86.avx2.psll.dq") {
+ // 128/256-bit shift left specified in bits.
unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
- Rep = UpgradeX86PSRLDQIntrinsics(Builder, C, CI->getArgOperand(0), 1,
+ Rep = UpgradeX86PSLLDQIntrinsics(Builder, C, CI->getArgOperand(0),
Shift / 8); // Shift is in bits.
- } else if (Name == "llvm.x86.avx2.psll.dq") {
- // 256-bit shift left specified in bits.
+ } else if (Name == "llvm.x86.sse2.psrl.dq" ||
+ Name == "llvm.x86.avx2.psrl.dq") {
+ // 128/256-bit shift right specified in bits.
unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
- Rep = UpgradeX86PSLLDQIntrinsics(Builder, C, CI->getArgOperand(0), 2,
+ Rep = UpgradeX86PSRLDQIntrinsics(Builder, C, CI->getArgOperand(0),
Shift / 8); // Shift is in bits.
- } else if (Name == "llvm.x86.avx2.psrl.dq") {
- // 256-bit shift right specified in bits.
- unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
- Rep = UpgradeX86PSRLDQIntrinsics(Builder, C, CI->getArgOperand(0), 2,
- Shift / 8); // Shift is in bits.
- } else if (Name == "llvm.x86.sse2.psll.dq.bs") {
- // 128-bit shift left specified in bytes.
- unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
- Rep = UpgradeX86PSLLDQIntrinsics(Builder, C, CI->getArgOperand(0), 1,
- Shift);
- } else if (Name == "llvm.x86.sse2.psrl.dq.bs") {
- // 128-bit shift right specified in bytes.
- unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
- Rep = UpgradeX86PSRLDQIntrinsics(Builder, C, CI->getArgOperand(0), 1,
- Shift);
- } else if (Name == "llvm.x86.avx2.psll.dq.bs") {
- // 256-bit shift left specified in bytes.
+ } else if (Name == "llvm.x86.sse2.psll.dq.bs" ||
+ Name == "llvm.x86.avx2.psll.dq.bs") {
+ // 128/256-bit shift left specified in bytes.
unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
- Rep = UpgradeX86PSLLDQIntrinsics(Builder, C, CI->getArgOperand(0), 2,
- Shift);
- } else if (Name == "llvm.x86.avx2.psrl.dq.bs") {
- // 256-bit shift right specified in bytes.
+ Rep = UpgradeX86PSLLDQIntrinsics(Builder, C, CI->getArgOperand(0), Shift);
+ } else if (Name == "llvm.x86.sse2.psrl.dq.bs" ||
+ Name == "llvm.x86.avx2.psrl.dq.bs") {
+ // 128/256-bit shift right specified in bytes.
unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
- Rep = UpgradeX86PSRLDQIntrinsics(Builder, C, CI->getArgOperand(0), 2,
- Shift);
+ Rep = UpgradeX86PSRLDQIntrinsics(Builder, C, CI->getArgOperand(0), Shift);
} else if (Name == "llvm.x86.sse41.pblendw" ||
Name == "llvm.x86.sse41.blendpd" ||
Name == "llvm.x86.sse41.blendps" ||
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