[PATCH] D20667: ARM: Add additional matching for UBFX instructions.

[Dave Green via llvm-commits]

dmgreen added a comment.

Hey James, cheers for taking a look at this.

For adding SBFX support; there might some cases to do with sign extending i16/i8's, but are probably quite limited in scope. The top bit of the AND would need to be set. Most such sequences of an AND+ASR are already either optimised to an AND+LSR, so will get caught by this change, or end up as just an ASR as the AND becomes superfluous.

This change was motivated by code like this:

  int example(unsigned int x, unsigned int *y) {
      if (x == 1) {
          return (*y & (1 << 5U)) != 0;
      } else if (x == 2) {
          return (*y & (1 << 6U)) != 0;
      }
      return 0;
  }

which was coming through as an AND+LSR. I made it a little more general to handle shifted mask AND operands, not just powers of 2, but in this case SBFX isn't as useful.


Repository:
  rL LLVM

http://reviews.llvm.org/D20667