[PATCH] D20591: [InstCombine] Catch more bswap cases missed due to zext and truncs.
Chad Rosier via llvm-commits
llvm-commits at lists.llvm.org
Thu May 26 06:40:20 PDT 2016
mcrosier added inline comments.
================
Comment at: test/Transforms/InstCombine/bswap.ll:106
@@ +105,3 @@
+ %conv = zext i16 %a to i32
+ %shr = lshr i16 %a, 8
+ %shl = shl i32 %conv, 8
----------------
gberry wrote:
> Shouldn't this be an i32 lshr of %conv and the second zext below deleted if you want the IR to look like it would for a target without i16 as a legal type?
With the exception of relabeling the variables and dropping irrelevant nsw/nuws, this is the code that is generated from this C test case when targeting AArch64:
unsigned short test16(unsigned short a) {
unsigned short b = (a & 0xff00) >> 8;
unsigned short c = (a & 0x00ff) << 8;
return b | c;
}
Produces:
define i16 @test16(i16 %a) #0 {
entry:
%conv = zext i16 %a to i32
%shr11 = lshr i16 %a, 8
%and3 = shl nuw nsw i32 %conv, 8
%conv5 = zext i16 %shr11 to i32
%or = or i32 %conv5, %and3
%conv7 = trunc i32 %or to i16
ret i16 %conv7
}
Regardless, I'm happy to add a test case similar to what you're suggesting.
http://reviews.llvm.org/D20591
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