[PATCH] D20522: [misched] Extend scheduler to handle unsupported features

[Simon Dardis via llvm-commits]

sdardis created this revision.
sdardis added subscribers: dsanders, llvm-commits.
sdardis set the repository for this revision to rL LLVM.

Currently isComplete = 1 requires that every instruction must
be described, declared unsupported or marked as having no
scheduling information for a processor.

For some backends such as MIPS, this requirement entails
long regex lists of instructions that are unsupported.

This patch teaches Tablegen to skip over instructions that
are associated with unsupported feature when checking if the
scheduling model is complete.

Patch by Daniel Sanders

Modification for checking for the existence of the predicate
done by myself.

Repository:
  rL LLVM

http://reviews.llvm.org/D20522

Files:
  include/llvm/Target/TargetSchedule.td
  lib/CodeGen/TargetSchedule.cpp
  utils/TableGen/CodeGenSchedule.cpp
  utils/TableGen/CodeGenSchedule.h

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