[llvm] r270415 - [AMDGPU] Assembler: refactor parsing of modifiers and immediates. Allow modifiers for imms.
Sam Kolton via llvm-commits
llvm-commits at lists.llvm.org
Mon May 23 02:59:14 PDT 2016
Author: skolton
Date: Mon May 23 04:59:02 2016
New Revision: 270415
URL: http://llvm.org/viewvc/llvm-project?rev=270415&view=rev
Log:
[AMDGPU] Assembler: refactor parsing of modifiers and immediates. Allow modifiers for imms.
Reviewers: nhaustov, tstellarAMD
Subscribers: kzhuravl, arsenm
Differential Revision: http://reviews.llvm.org/D20166
Modified:
llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
llvm/trunk/test/MC/AMDGPU/ds-err.s
llvm/trunk/test/MC/AMDGPU/flat-scratch.s
llvm/trunk/test/MC/AMDGPU/out-of-range-registers.s
llvm/trunk/test/MC/AMDGPU/smrd-err.s
llvm/trunk/test/MC/AMDGPU/smrd.s
llvm/trunk/test/MC/AMDGPU/sop1-err.s
llvm/trunk/test/MC/AMDGPU/sop1.s
llvm/trunk/test/MC/AMDGPU/sop2.s
llvm/trunk/test/MC/AMDGPU/vop3.s
Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=270415&r1=270414&r2=270415&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Mon May 23 04:59:02 2016
@@ -180,8 +180,29 @@ public:
const MCExpr *Expr;
};
- void addImmOperands(MCInst &Inst, unsigned N) const {
- Inst.addOperand(MCOperand::createImm(getImm()));
+ void addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers = true) const {
+ if (Imm.Type == ImmTyNone && ApplyModifiers && Imm.Modifiers != 0) {
+ // Apply modifiers to immediate value
+ int64_t Val = Imm.Val;
+ bool Negate = Imm.Modifiers & 0x1;
+ bool Abs = Imm.Modifiers & 0x2;
+ if (Imm.IsFPImm) {
+ APFloat F(BitsToFloat(Val));
+ if (Abs) {
+ F.clearSign();
+ }
+ if (Negate) {
+ F.changeSign();
+ }
+ Val = F.bitcastToAPInt().getZExtValue();
+ } else {
+ Val = Abs ? std::abs(Val) : Val;
+ Val = Negate ? -Val : Val;
+ }
+ Inst.addOperand(MCOperand::createImm(Val));
+ } else {
+ Inst.addOperand(MCOperand::createImm(getImm()));
+ }
}
StringRef getToken() const {
@@ -205,7 +226,7 @@ public:
addRegOperands(Inst, N);
} else {
Inst.addOperand(MCOperand::createImm(Imm.Modifiers));
- addImmOperands(Inst, N);
+ addImmOperands(Inst, N, false);
}
}
@@ -646,6 +667,10 @@ public:
OperandVector &Operands);
OperandMatchResultTy parseStringWithPrefix(const char *Prefix, StringRef &Value);
+ OperandMatchResultTy parseImm(OperandVector &Operands);
+ OperandMatchResultTy parseRegOrImm(OperandVector &Operands);
+ OperandMatchResultTy parseRegOrImmWithInputMods(OperandVector &Operands);
+
OperandMatchResultTy parseOptionalOperand(OperandVector &Operands, const OptionalOperand& Op, bool AddDefault);
OperandMatchResultTy parseAMDGPUOperand(OperandVector &Operands, StringRef Name);
@@ -938,6 +963,131 @@ std::unique_ptr<AMDGPUOperand> AMDGPUAsm
TRI, &getSTI(), false);
}
+AMDGPUAsmParser::OperandMatchResultTy
+AMDGPUAsmParser::parseImm(OperandVector &Operands) {
+ bool Minus = false;
+ if (getLexer().getKind() == AsmToken::Minus) {
+ Minus = true;
+ Parser.Lex();
+ }
+
+ SMLoc S = Parser.getTok().getLoc();
+ switch(getLexer().getKind()) {
+ case AsmToken::Integer: {
+ int64_t IntVal;
+ if (getParser().parseAbsoluteExpression(IntVal))
+ return MatchOperand_ParseFail;
+ if (!isInt<32>(IntVal) && !isUInt<32>(IntVal)) {
+ Error(S, "invalid immediate: only 32-bit values are legal");
+ return MatchOperand_ParseFail;
+ }
+
+ if (Minus)
+ IntVal *= -1;
+ Operands.push_back(AMDGPUOperand::CreateImm(IntVal, S));
+ return MatchOperand_Success;
+ }
+ case AsmToken::Real: {
+ // FIXME: We should emit an error if a double precisions floating-point
+ // value is used. I'm not sure the best way to detect this.
+ int64_t IntVal;
+ if (getParser().parseAbsoluteExpression(IntVal))
+ return MatchOperand_ParseFail;
+
+ APFloat F((float)BitsToDouble(IntVal));
+ if (Minus)
+ F.changeSign();
+ Operands.push_back(
+ AMDGPUOperand::CreateImm(F.bitcastToAPInt().getZExtValue(), S,
+ AMDGPUOperand::ImmTyNone, true));
+ return MatchOperand_Success;
+ }
+ default:
+ return Minus ? MatchOperand_ParseFail : MatchOperand_NoMatch;
+ }
+}
+
+AMDGPUAsmParser::OperandMatchResultTy
+AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands) {
+ auto res = parseImm(Operands);
+ if (res != MatchOperand_NoMatch) {
+ return res;
+ }
+
+ if (auto R = parseRegister()) {
+ assert(R->isReg());
+ R->Reg.IsForcedVOP3 = isForcedVOP3();
+ Operands.push_back(std::move(R));
+ return MatchOperand_Success;
+ }
+ return MatchOperand_ParseFail;
+}
+
+AMDGPUAsmParser::OperandMatchResultTy
+AMDGPUAsmParser::parseRegOrImmWithInputMods(OperandVector &Operands) {
+ // XXX: During parsing we can't determine if minus sign means
+ // negate-modifier or negative immediate value.
+ // By default we suppose it is modifier.
+ bool Negate = false, Abs = false, Abs2 = false;
+
+ if (getLexer().getKind()== AsmToken::Minus) {
+ Parser.Lex();
+ Negate = true;
+ }
+
+ if (getLexer().getKind() == AsmToken::Identifier && Parser.getTok().getString() == "abs") {
+ Parser.Lex();
+ Abs2 = true;
+ if (getLexer().isNot(AsmToken::LParen)) {
+ Error(Parser.getTok().getLoc(), "expected left paren after abs");
+ return MatchOperand_ParseFail;
+ }
+ Parser.Lex();
+ }
+
+ if (getLexer().getKind() == AsmToken::Pipe) {
+ if (Abs2) {
+ Error(Parser.getTok().getLoc(), "expected register or immediate");
+ return MatchOperand_ParseFail;
+ }
+ Parser.Lex();
+ Abs = true;
+ }
+
+ auto Res = parseRegOrImm(Operands);
+ if (Res != MatchOperand_Success) {
+ return Res;
+ }
+
+ unsigned Modifiers = 0;
+ if (Negate) {
+ Modifiers |= 0x1;
+ }
+ if (Abs) {
+ if (getLexer().getKind() != AsmToken::Pipe) {
+ Error(Parser.getTok().getLoc(), "expected vertical bar");
+ return MatchOperand_ParseFail;
+ }
+ Parser.Lex();
+ Modifiers |= 0x2;
+ }
+ if (Abs2) {
+ if (getLexer().isNot(AsmToken::RParen)) {
+ Error(Parser.getTok().getLoc(), "expected closing parentheses");
+ return MatchOperand_ParseFail;
+ }
+ Parser.Lex();
+ Modifiers |= 0x2;
+ }
+
+ if (Modifiers) {
+ AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
+ Op.setModifiers(Modifiers);
+ }
+ return MatchOperand_Success;
+}
+
+
unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
@@ -1272,111 +1422,22 @@ AMDGPUAsmParser::parseOperand(OperandVec
// If we are parsing after we reach EndOfStatement then this means we
// are appending default values to the Operands list. This is only done
// by custom parser, so we shouldn't continue on to the generic parsing.
- if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail||
+ if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail ||
getLexer().is(AsmToken::EndOfStatement))
return ResTy;
- bool Negate = false, Abs = false, Abs2 = false;
+ ResTy = parseRegOrImm(Operands);
- if (getLexer().getKind()== AsmToken::Minus) {
- Parser.Lex();
- Negate = true;
- }
-
- if (getLexer().getKind() == AsmToken::Identifier && Parser.getTok().getString() == "abs") {
- Parser.Lex();
- Abs2 = true;
- if (getLexer().isNot(AsmToken::LParen)) {
- Error(Parser.getTok().getLoc(), "expected left paren after abs");
- return MatchOperand_ParseFail;
- }
- Parser.Lex();
- }
+ if (ResTy == MatchOperand_Success)
+ return ResTy;
- if (getLexer().getKind() == AsmToken::Pipe) {
+ if (getLexer().getKind() == AsmToken::Identifier) {
+ const auto &Tok = Parser.getTok();
+ Operands.push_back(AMDGPUOperand::CreateToken(Tok.getString(), Tok.getLoc()));
Parser.Lex();
- Abs = true;
- }
-
- switch(getLexer().getKind()) {
- case AsmToken::Integer: {
- SMLoc S = Parser.getTok().getLoc();
- int64_t IntVal;
- if (getParser().parseAbsoluteExpression(IntVal))
- return MatchOperand_ParseFail;
- if (!isInt<32>(IntVal) && !isUInt<32>(IntVal)) {
- Error(S, "invalid immediate: only 32-bit values are legal");
- return MatchOperand_ParseFail;
- }
-
- if (Negate)
- IntVal *= -1;
- Operands.push_back(AMDGPUOperand::CreateImm(IntVal, S));
- return MatchOperand_Success;
- }
- case AsmToken::Real: {
- // FIXME: We should emit an error if a double precisions floating-point
- // value is used. I'm not sure the best way to detect this.
- SMLoc S = Parser.getTok().getLoc();
- int64_t IntVal;
- if (getParser().parseAbsoluteExpression(IntVal))
- return MatchOperand_ParseFail;
-
- APFloat F((float)BitsToDouble(IntVal));
- if (Negate)
- F.changeSign();
- Operands.push_back(
- AMDGPUOperand::CreateImm(F.bitcastToAPInt().getZExtValue(), S));
- return MatchOperand_Success;
- }
- case AsmToken::LBrac:
- case AsmToken::Identifier: {
- if (auto R = parseRegister()) {
- unsigned Modifiers = 0;
-
- if (Negate)
- Modifiers |= 0x1;
-
- if (Abs) {
- if (getLexer().getKind() != AsmToken::Pipe)
- return MatchOperand_ParseFail;
- Parser.Lex();
- Modifiers |= 0x2;
- }
- if (Abs2) {
- if (getLexer().isNot(AsmToken::RParen)) {
- return MatchOperand_ParseFail;
- }
- Parser.Lex();
- Modifiers |= 0x2;
- }
- assert(R->isReg());
- R->Reg.IsForcedVOP3 = isForcedVOP3();
- if (Modifiers) {
- R->setModifiers(Modifiers);
- }
- Operands.push_back(std::move(R));
- } else {
- if (ResTy == MatchOperand_NoMatch) {
- const auto &Tok = Parser.getTok();
- Operands.push_back(AMDGPUOperand::CreateToken(Tok.getString(),
- Tok.getLoc()));
- Parser.Lex();
- if (getLexer().is(AsmToken::Colon)) {
- Parser.Lex();
- if (getLexer().is(AsmToken::Identifier)) {
- Parser.Lex();
- }
- }
- } else {
- return ResTy;
- }
- }
- return MatchOperand_Success;
- }
- default:
- return MatchOperand_NoMatch;
+ return MatchOperand_Success;
}
+ return MatchOperand_NoMatch;
}
bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
@@ -1404,13 +1465,21 @@ bool AMDGPUAsmParser::ParseInstruction(P
// Eat the comma or space if there is one.
if (getLexer().is(AsmToken::Comma))
Parser.Lex();
-
+
switch (Res) {
case MatchOperand_Success: break;
- case MatchOperand_ParseFail: return Error(getLexer().getLoc(),
- "failed parsing operand.");
- case MatchOperand_NoMatch: return Error(getLexer().getLoc(),
- "not a valid operand.");
+ case MatchOperand_ParseFail:
+ Error(getLexer().getLoc(), "failed parsing operand.");
+ while (!getLexer().is(AsmToken::EndOfStatement)) {
+ Parser.Lex();
+ }
+ return true;
+ case MatchOperand_NoMatch:
+ Error(getLexer().getLoc(), "not a valid operand.");
+ while (!getLexer().is(AsmToken::EndOfStatement)) {
+ Parser.Lex();
+ }
+ return true;
}
}
@@ -2188,6 +2257,75 @@ AMDGPUAsmParser::parseLWE(OperandVector
return parseNamedBit("lwe", Operands, AMDGPUOperand::ImmTyLWE);
}
+void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands) {
+ unsigned I = 1;
+ const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
+ for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
+ ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
+ }
+
+ OptionalImmIndexMap OptionalIdx;
+
+ for (unsigned E = Operands.size(); I != E; ++I) {
+ AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
+
+ // Add the register arguments
+ if (Op.isRegOrImm()) {
+ Op.addRegOrImmOperands(Inst, 1);
+ continue;
+ } else if (Op.isImmModifier()) {
+ OptionalIdx[Op.getImmTy()] = I;
+ } else {
+ assert(false);
+ }
+ }
+
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128);
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
+}
+
+void AMDGPUAsmParser::cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands) {
+ unsigned I = 1;
+ const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
+ for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
+ ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
+ }
+
+ // Add src, same as dst
+ ((AMDGPUOperand &)*Operands[I]).addRegOperands(Inst, 1);
+
+ OptionalImmIndexMap OptionalIdx;
+
+ for (unsigned E = Operands.size(); I != E; ++I) {
+ AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
+
+ // Add the register arguments
+ if (Op.isRegOrImm()) {
+ Op.addRegOrImmOperands(Inst, 1);
+ continue;
+ } else if (Op.isImmModifier()) {
+ OptionalIdx[Op.getImmTy()] = I;
+ } else {
+ assert(false);
+ }
+ }
+
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128);
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
+ addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
+}
+
AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDMask() const {
return AMDGPUOperand::CreateImm(0, SMLoc(), AMDGPUOperand::ImmTyDMask);
}
@@ -2406,75 +2544,6 @@ void AMDGPUAsmParser::cvtVOP3(MCInst &In
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
}
-void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands) {
- unsigned I = 1;
- const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
- for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
- ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
- }
-
- OptionalImmIndexMap OptionalIdx;
-
- for (unsigned E = Operands.size(); I != E; ++I) {
- AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
-
- // Add the register arguments
- if (Op.isRegOrImm()) {
- Op.addRegOrImmOperands(Inst, 1);
- continue;
- } else if (Op.isImmModifier()) {
- OptionalIdx[Op.getImmTy()] = I;
- } else {
- assert(false);
- }
- }
-
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
-}
-
-void AMDGPUAsmParser::cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands) {
- unsigned I = 1;
- const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
- for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
- ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
- }
-
- // Add src, same as dst
- ((AMDGPUOperand &)*Operands[I]).addRegOperands(Inst, 1);
-
- OptionalImmIndexMap OptionalIdx;
-
- for (unsigned E = Operands.size(); I != E; ++I) {
- AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
-
- // Add the register arguments
- if (Op.isRegOrImm()) {
- Op.addRegOrImmOperands(Inst, 1);
- continue;
- } else if (Op.isImmModifier()) {
- OptionalIdx[Op.getImmTy()] = I;
- } else {
- assert(false);
- }
- }
-
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
-}
-
//===----------------------------------------------------------------------===//
// dpp
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=270415&r1=270414&r2=270415&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Mon May 23 04:59:02 2016
@@ -1098,6 +1098,7 @@ def InputMods : OperandWithDefaultOps <i
def InputModsMatchClass : AsmOperandClass {
let Name = "RegOrImmWithInputMods";
+ let ParserMethod = "parseRegOrImmWithInputMods";
}
def InputModsNoDefault : Operand <i32> {
Modified: llvm/trunk/test/MC/AMDGPU/ds-err.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/ds-err.s?rev=270415&r1=270414&r2=270415&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/ds-err.s (original)
+++ llvm/trunk/test/MC/AMDGPU/ds-err.s Mon May 23 04:59:02 2016
@@ -6,11 +6,11 @@
ds_add_u32 v2, v4 offset:1000000000
// offset0 twice
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand.
ds_write2_b32 v2, v4, v6 offset0:4 offset0:8
// offset1 twice
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand.
ds_write2_b32 v2, v4, v6 offset1:4 offset1:8
// offset0 too big
Modified: llvm/trunk/test/MC/AMDGPU/flat-scratch.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/flat-scratch.s?rev=270415&r1=270414&r2=270415&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/flat-scratch.s (original)
+++ llvm/trunk/test/MC/AMDGPU/flat-scratch.s Mon May 23 04:59:02 2016
@@ -1,33 +1,36 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=SI -check-prefix=GCN %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=NOCI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=NOVI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s | FileCheck -check-prefix=CI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
-// Add a different RUN line for the failing checks, because when stderr and stdout are mixed the
-// order things are printed is not deterministic.
-// RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
-
s_mov_b64 flat_scratch, -1
-// SI: error: invalid operand for instruction
+// NOSI: error: not a valid operand.
// CI: s_mov_b64 flat_scratch, -1 ; encoding: [0xc1,0x04,0xe8,0xbe]
// VI: s_mov_b64 flat_scratch, -1 ; encoding: [0xc1,0x01,0xe6,0xbe]
s_mov_b32 flat_scratch_lo, -1
-// SI: error: invalid operand for instruction
+// NOSI: error: not a valid operand.
// CI: s_mov_b32 flat_scratch_lo, -1 ; encoding: [0xc1,0x03,0xe8,0xbe]
// VI: s_mov_b32 flat_scratch_lo, -1 ; encoding: [0xc1,0x00,0xe6,0xbe]
s_mov_b32 flat_scratch_hi, -1
-// SI: error: invalid operand for instruction
+// NOSI: error: not a valid operand.
// CI: s_mov_b32 flat_scratch_hi, -1 ; encoding: [0xc1,0x03,0xe9,0xbe]
// VI: s_mov_b32 flat_scratch_hi, -1 ; encoding: [0xc1,0x00,0xe7,0xbe]
s_mov_b64 flat_scratch_lo, -1
-// GCN: error: invalid operand for instruction
+// NOSI: error: not a valid operand.
+// NOCI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
s_mov_b64 flat_scratch_hi, -1
-// GCN: error: invalid operand for instruction
+// NOSI: error: not a valid operand.
+// NOCI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
s_mov_b32 flat_scratch, -1
-// GCN: error: invalid operand for instruction
+// NOSI: error: not a valid operand.
+// NOCI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/AMDGPU/out-of-range-registers.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/out-of-range-registers.s?rev=270415&r1=270414&r2=270415&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/out-of-range-registers.s (original)
+++ llvm/trunk/test/MC/AMDGPU/out-of-range-registers.s Mon May 23 04:59:02 2016
@@ -2,61 +2,61 @@
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s
s_add_i32 s104, s0, s1
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_add_i32 s105, s0, s1
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
v_add_i32 v256, v0, v1
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
v_add_i32 v257, v0, v1
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_mov_b64 s[0:17], -1
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_mov_b64 s[103:104], -1
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_mov_b64 s[104:105], -1
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_load_dwordx4 s[102:105], s[2:3], s4
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_load_dwordx4 s[104:108], s[2:3], s4
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_load_dwordx4 s[108:112], s[2:3], s4
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_load_dwordx4 s[1:4], s[2:3], s4
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_load_dwordx4 s[1:4], s[2:3], s4
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_load_dwordx8 s[104:111], s[2:3], s4
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_load_dwordx8 s[100:107], s[2:3], s4
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_load_dwordx8 s[108:115], s[2:3], s4
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_load_dwordx16 s[92:107], s[2:3], s4
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_load_dwordx16 s[96:111], s[2:3], s4
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_load_dwordx16 s[100:115], s[2:3], s4
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_load_dwordx16 s[104:119], s[2:3], s4
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
s_load_dwordx16 s[108:123], s[2:3], s4
-// CHECK: error: invalid operand for instruction
+// CHECK: error: not a valid operand
Modified: llvm/trunk/test/MC/AMDGPU/smrd-err.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/smrd-err.s?rev=270415&r1=270414&r2=270415&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/smrd-err.s (original)
+++ llvm/trunk/test/MC/AMDGPU/smrd-err.s Mon May 23 04:59:02 2016
@@ -2,14 +2,14 @@
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
s_load_dwordx4 s[100:103], s[2:3], s4
-// VI: error: invalid operand for instruction
+// VI: error: not a valid operand
// SI: s_load_dwordx4 s[100:103], s[2:3], s4
s_load_dwordx8 s[96:103], s[2:3], s4
-// VI: error: invalid operand for instruction
+// VI: error: not a valid operand
// SI: s_load_dwordx8 s[96:103], s[2:3], s4
s_load_dwordx16 s[88:103], s[2:3], s4
-// VI: error: invalid operand for instruction
+// VI: error: not a valid operand
// SI: s_load_dwordx16 s[88:103], s[2:3], s4
Modified: llvm/trunk/test/MC/AMDGPU/smrd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/smrd.s?rev=270415&r1=270414&r2=270415&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/smrd.s (original)
+++ llvm/trunk/test/MC/AMDGPU/smrd.s Mon May 23 04:59:02 2016
@@ -58,7 +58,7 @@ s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttm
s_load_dwordx4 s[100:103], s[2:3], s4
// GCN: s_load_dwordx4 s[100:103], s[2:3], s4 ; encoding: [0x04,0x02,0xb2,0xc0]
-// NOVI: error: invalid operand for instruction
+// NOVI: error: not a valid operand
s_load_dwordx8 s[8:15], s[2:3], 1
// GCN: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x03,0xc4,0xc0]
@@ -70,7 +70,7 @@ s_load_dwordx8 s[8:15], s[2:3], s4
s_load_dwordx8 s[96:103], s[2:3], s4
// GCN: s_load_dwordx8 s[96:103], s[2:3], s4 ; encoding: [0x04,0x02,0xf0,0xc0]
-// NOVI: error: invalid operand for instruction
+// NOVI: error: not a valid operand
s_load_dwordx16 s[16:31], s[2:3], 1
// GCN: s_load_dwordx16 s[16:31], s[2:3], 0x1 ; encoding: [0x01,0x03,0x08,0xc1]
@@ -82,7 +82,7 @@ s_load_dwordx16 s[16:31], s[2:3], s4
s_load_dwordx16 s[88:103], s[2:3], s4
// GCN: s_load_dwordx16 s[88:103], s[2:3], s4 ; encoding: [0x04,0x02,0x2c,0xc1]
-// NOVI: error: invalid operand for instruction
+// NOVI: error: not a valid operand
s_buffer_load_dword s1, s[4:7], 1
// GCN: s_buffer_load_dword s1, s[4:7], 0x1 ; encoding: [0x01,0x85,0x00,0xc2]
@@ -118,7 +118,7 @@ s_buffer_load_dwordx4 ttmp[8:11], ttmp[4
s_buffer_load_dwordx4 s[100:103], s[4:7], s4
// GCN: s_buffer_load_dwordx4 s[100:103], s[4:7], s4 ; encoding: [0x04,0x04,0xb2,0xc2]
-// NOVI: error: invalid operand for instruction
+// NOVI: error: not a valid operand
s_buffer_load_dwordx8 s[8:15], s[4:7], 1
// GCN: s_buffer_load_dwordx8 s[8:15], s[4:7], 0x1 ; encoding: [0x01,0x05,0xc4,0xc2]
@@ -130,7 +130,7 @@ s_buffer_load_dwordx8 s[8:15], s[4:7], s
s_buffer_load_dwordx8 s[96:103], s[4:7], s4
// GCN: s_buffer_load_dwordx8 s[96:103], s[4:7], s4 ; encoding: [0x04,0x04,0xf0,0xc2]
-// NOVI: error: invalid operand for instruction
+// NOVI: error: not a valid operand
s_buffer_load_dwordx16 s[16:31], s[4:7], 1
// GCN: s_buffer_load_dwordx16 s[16:31], s[4:7], 0x1 ; encoding: [0x01,0x05,0x08,0xc3]
@@ -142,7 +142,7 @@ s_buffer_load_dwordx16 s[16:31], s[4:7],
s_buffer_load_dwordx16 s[88:103], s[4:7], s4
// GCN: s_buffer_load_dwordx16 s[88:103], s[4:7], s4 ; encoding: [0x04,0x04,0x2c,0xc3]
-// NOVI: error: invalid operand for instruction
+// NOVI: error: not a valid operand
s_dcache_inv
// GCN: s_dcache_inv ; encoding: [0x00,0x00,0xc0,0xc7]
Modified: llvm/trunk/test/MC/AMDGPU/sop1-err.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/sop1-err.s?rev=270415&r1=270414&r2=270415&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/sop1-err.s (original)
+++ llvm/trunk/test/MC/AMDGPU/sop1-err.s Mon May 23 04:59:02 2016
@@ -9,16 +9,16 @@ s_mov_b32 s1, v0
// GCN: error: invalid operand for instruction
s_mov_b32 s[1:2], s0
-// GCN: error: invalid operand for instruction
+// GCN: error: not a valid operand
s_mov_b32 s0, s[1:2]
-// GCN: error: invalid operand for instruction
+// GCN: error: not a valid operand
s_mov_b32 s220, s0
-// GCN: error: invalid operand for instruction
+// GCN: error: not a valid operand
s_mov_b32 s0, s220
-// GCN: error: invalid operand for instruction
+// GCN: error: not a valid operand
s_mov_b64 s1, s[0:1]
// GCN: error: invalid operand for instruction
@@ -34,28 +34,22 @@ s_mov_b32 s1, 0xfffffffff
s_mov_b64 s[0:1], 0xfffffffff
// GCN: error: invalid immediate: only 32-bit values are legal
-s_mov_b64 s[0:1], 0xfffffffff
-// GCN: error: invalid immediate: only 32-bit values are legal
-
-s_mov_b64 s[0:1], 0xfffffffff
-// GCN: error: invalid immediate: only 32-bit values are legal
-
s_mov_b64 s[0:1], 0x0000000200000000
// GCN: error: invalid immediate: only 32-bit values are legal
// FIXME: This shoudl probably say failed to parse.
s_mov_b32 s
-// GCN: error: invalid operand for instruction
+// GCN: error: not a valid operand
// Out of range register
s_mov_b32 s102, 1
-// VI: error: invalid operand for instruction
-// SI-NOT: error
+// VI: error: not a valid operand
+// SI: s_mov_b32 s102, 1
s_mov_b32 s103, 1
-// VI: error: invalid operand for instruction
-// SI-NOT: error
+// VI: error: not a valid operand
+// SI: s_mov_b32 s103, 1
s_mov_b64 s[102:103], -1
-// VI: error: invalid operand for instruction
-// SI-NOT: error
+// VI: error: not a valid operand
+// SI: s_mov_b64 s[102:103], -1
Modified: llvm/trunk/test/MC/AMDGPU/sop1.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/sop1.s?rev=270415&r1=270414&r2=270415&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/sop1.s (original)
+++ llvm/trunk/test/MC/AMDGPU/sop1.s Mon May 23 04:59:02 2016
@@ -43,7 +43,7 @@ s_mov_b64 s[0:1], 0x80000000
s_mov_b64 s[102:103], -1
// SICI: s_mov_b64 s[102:103], -1 ; encoding: [0xc1,0x04,0xe6,0xbe]
-// NOVI: error: invalid operand for instruction
+// NOVI: error: not a valid operand
s_cmov_b32 s1, 200
// SICI: s_cmov_b32 s1, 0xc8 ; encoding: [0xff,0x05,0x81,0xbe,0xc8,0x00,0x00,0x00]
Modified: llvm/trunk/test/MC/AMDGPU/sop2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/sop2.s?rev=270415&r1=270414&r2=270415&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/sop2.s (original)
+++ llvm/trunk/test/MC/AMDGPU/sop2.s Mon May 23 04:59:02 2016
@@ -166,4 +166,4 @@ s_absdiff_i32 s2, s4, s6
s_add_u32 s101, s102, s103
// SICI: s_add_u32 s101, s102, s103 ; encoding: [0x66,0x67,0x65,0x80]
-// NOVI: error: invalid operand for instruction
+// NOVI: error: not a valid operand
Modified: llvm/trunk/test/MC/AMDGPU/vop3.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/vop3.s?rev=270415&r1=270414&r2=270415&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/vop3.s (original)
+++ llvm/trunk/test/MC/AMDGPU/vop3.s Mon May 23 04:59:02 2016
@@ -339,8 +339,8 @@ v_div_scale_f32 v24, vcc, v22, 1.0, v22
// VI: v_div_scale_f32 v24, vcc, v22, 1.0, v22 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0xe5,0x59,0x04]
v_div_scale_f32 v24, vcc, v22, v22, -2.0
-// SICI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xda,0xd2,0x16,0x2d,0xd6,0x03]
-// VI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0x2d,0xd6,0x03]
+// SICI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xda,0xd2,0x16,0x2d,0xd2,0x83]
+// VI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0x2d,0xd2,0x83]
v_div_scale_f32 v24, vcc, v22, v22, 0xc0000000
// SICI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xda,0xd2,0x16,0x2d,0xd6,0x03]
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