[PATCH] D20508: AMDGPU: Fix v2i64/v2f64 bitcasts
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri May 20 23:51:21 PDT 2016
arsenm created this revision.
arsenm added a reviewer: tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added subscribers: kzhuravl, arsenm.
These operations tend to get promoted away to v4i32 so
this doesn't happen often.
http://reviews.llvm.org/D20508
Files:
lib/Target/AMDGPU/SIInstructions.td
test/CodeGen/AMDGPU/bitcast.ll
Index: test/CodeGen/AMDGPU/bitcast.ll
===================================================================
--- test/CodeGen/AMDGPU/bitcast.ll
+++ test/CodeGen/AMDGPU/bitcast.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; This test just checks that the compiler doesn't crash.
@@ -75,3 +75,35 @@
store <2 x i32> %bc, <2 x i32> addrspace(1)* %out, align 8
ret void
}
+
+; FUNC-LABEL: {{^}}bitcast_v2i64_to_v2f64:
+define void @bitcast_v2i64_to_v2f64(i32 %cond, <2 x double> addrspace(1)* %out, <2 x i64> %value) {
+entry:
+ %cmp0 = icmp eq i32 %cond, 0
+ br i1 %cmp0, label %if, label %end
+
+if:
+ %cast = bitcast <2 x i64> %value to <2 x double>
+ br label %end
+
+end:
+ %phi = phi <2 x double> [zeroinitializer, %entry], [%cast, %if]
+ store <2 x double> %phi, <2 x double> addrspace(1)* %out
+ ret void
+}
+
+; FUNC-LABEL: {{^}}bitcast_v2f64_to_v2i64:
+define void @bitcast_v2f64_to_v2i64(i32 %cond, <2 x i64> addrspace(1)* %out, <2 x double> %value) {
+entry:
+ %cmp0 = icmp eq i32 %cond, 0
+ br i1 %cmp0, label %if, label %end
+
+if:
+ %cast = bitcast <2 x double> %value to <2 x i64>
+ br label %end
+
+end:
+ %phi = phi <2 x i64> [zeroinitializer, %entry], [%cast, %if]
+ store <2 x i64> %phi, <2 x i64> addrspace(1)* %out
+ ret void
+}
Index: lib/Target/AMDGPU/SIInstructions.td
===================================================================
--- lib/Target/AMDGPU/SIInstructions.td
+++ lib/Target/AMDGPU/SIInstructions.td
@@ -2873,6 +2873,8 @@
def : BitConvert <v2f64, v4i32, VReg_128>;
def : BitConvert <v4f32, v2f64, VReg_128>;
def : BitConvert <v4i32, v2f64, VReg_128>;
+def : BitConvert <v2i64, v2f64, VReg_128>;
+def : BitConvert <v2f64, v2i64, VReg_128>;
// 256-bit bitcast
def : BitConvert <v8i32, v8f32, SReg_256>;
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