[PATCH] D20310: Teach LLVM about Power 9 D-Form VSX Instructions

Chuang-Yu Cheng via llvm-commits llvm-commits at lists.llvm.org
Fri May 20 16:59:51 PDT 2016


cycheng added a comment.

> Unfortunately, this still isn't quite the correct semantics. Although this will target the right physical registers, the encoding is wrong. These really are VR registers and have 5-bit fields in the encoding. Things like:

> 

>   lxsd 35, 8(3)

> 

> are not likely to produce the desired results. These instructions need the VR register to be specified in the 0-31 range which will actually mean VSR 32-63.

>  As far as I can tell, the idea with these instructions is that we get scalar floating point values using the nice D-Form loads into the remaining VSR's (the FP D-Form loads can be used for VSRs 0-31).

> 

> I think perhaps the best way to handle these would be to define a new register class which will alias the VRRC registers, but has 64-bit spill size and can hold f64/f32.


Oh.. I see my mistake, thanks! I will fix this by defining a new register class.


http://reviews.llvm.org/D20310





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