[llvm] r270283 - SDAG: Implement Select instead of SelectImpl in PPCDAGToDAGISel
Justin Bogner via llvm-commits
llvm-commits at lists.llvm.org
Fri May 20 14:43:24 PDT 2016
Author: bogner
Date: Fri May 20 16:43:23 2016
New Revision: 270283
URL: http://llvm.org/viewvc/llvm-project?rev=270283&view=rev
Log:
SDAG: Implement Select instead of SelectImpl in PPCDAGToDAGISel
- Where we were returning a node before, call ReplaceNode instead.
- Where we would return null to fall back to another selector, rename
the method to try* and return a bool for success.
- Where we were calling SelectNodeTo, just return afterwards.
Part of llvm.org/pr26808.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=270283&r1=270282&r2=270283&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri May 20 16:43:23 2016
@@ -122,14 +122,14 @@ namespace {
/// base register. Return the virtual register that holds this value.
SDNode *getGlobalBaseReg();
- SDNode *getFrameIndex(SDNode *SN, SDNode *N, unsigned Offset = 0);
+ void selectFrameIndex(SDNode *SN, SDNode *N, unsigned Offset = 0);
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
- SDNode *SelectImpl(SDNode *N) override;
+ void Select(SDNode *N) override;
- SDNode *SelectBitfieldInsert(SDNode *N);
- SDNode *SelectBitPermutation(SDNode *N);
+ bool tryBitfieldInsert(SDNode *N);
+ bool tryBitPermutation(SDNode *N);
/// SelectCC - Select a comparison of the specified values with the
/// specified condition code, returning the CR# of the expression.
@@ -228,7 +228,7 @@ namespace {
#include "PPCGenDAGISel.inc"
private:
- SDNode *SelectSETCC(SDNode *N);
+ bool trySETCC(SDNode *N);
void PeepholePPC64();
void PeepholePPC64ZExt();
@@ -240,7 +240,7 @@ private:
bool AllUsersSelectZero(SDNode *N);
void SwapAllSelectUsers(SDNode *N);
- SDNode *transferMemOperands(SDNode *N, SDNode *Result);
+ void transferMemOperands(SDNode *N, SDNode *Result);
};
}
@@ -458,16 +458,17 @@ static bool isOpcWithIntImmediate(SDNode
&& isInt32Immediate(N->getOperand(1).getNode(), Imm);
}
-SDNode *PPCDAGToDAGISel::getFrameIndex(SDNode *SN, SDNode *N, unsigned Offset) {
+void PPCDAGToDAGISel::selectFrameIndex(SDNode *SN, SDNode *N, unsigned Offset) {
SDLoc dl(SN);
int FI = cast<FrameIndexSDNode>(N)->getIndex();
SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
if (SN->hasOneUse())
- return CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI,
- getSmallIPtrImm(Offset, dl));
- return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
- getSmallIPtrImm(Offset, dl));
+ CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI,
+ getSmallIPtrImm(Offset, dl));
+ else
+ ReplaceNode(SN, CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
+ getSmallIPtrImm(Offset, dl)));
}
bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
@@ -512,9 +513,9 @@ bool PPCDAGToDAGISel::isRotateAndMask(SD
return false;
}
-/// SelectBitfieldInsert - turn an or of two masked values into
-/// the rotate left word immediate then mask insert (rlwimi) instruction.
-SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
+/// Turn an or of two masked values into the rotate left word immediate then
+/// mask insert (rlwimi) instruction.
+bool PPCDAGToDAGISel::tryBitfieldInsert(SDNode *N) {
SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1);
SDLoc dl(N);
@@ -584,15 +585,16 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldI
SH &= 31;
SDValue Ops[] = { Op0, Op1, getI32Imm(SH, dl), getI32Imm(MB, dl),
getI32Imm(ME, dl) };
- return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops));
+ return true;
}
}
- return nullptr;
+ return false;
}
// Predict the number of instructions that would be generated by calling
-// SelectInt64(N).
-static unsigned SelectInt64CountDirect(int64_t Imm) {
+// getInt64(N).
+static unsigned getInt64CountDirect(int64_t Imm) {
// Assume no remaining bits.
unsigned Remainder = 0;
// Assume no shift required.
@@ -653,17 +655,17 @@ static uint64_t Rot64(uint64_t Imm, unsi
return (Imm << R) | (Imm >> (64 - R));
}
-static unsigned SelectInt64Count(int64_t Imm) {
- unsigned Count = SelectInt64CountDirect(Imm);
+static unsigned getInt64Count(int64_t Imm) {
+ unsigned Count = getInt64CountDirect(Imm);
if (Count == 1)
return Count;
for (unsigned r = 1; r < 63; ++r) {
uint64_t RImm = Rot64(Imm, r);
- unsigned RCount = SelectInt64CountDirect(RImm) + 1;
+ unsigned RCount = getInt64CountDirect(RImm) + 1;
Count = std::min(Count, RCount);
- // See comments in SelectInt64 for an explanation of the logic below.
+ // See comments in getInt64 for an explanation of the logic below.
unsigned LS = findLastSet(RImm);
if (LS != r-1)
continue;
@@ -671,16 +673,16 @@ static unsigned SelectInt64Count(int64_t
uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
uint64_t RImmWithOnes = RImm | OnesMask;
- RCount = SelectInt64CountDirect(RImmWithOnes) + 1;
+ RCount = getInt64CountDirect(RImmWithOnes) + 1;
Count = std::min(Count, RCount);
}
return Count;
}
-// Select a 64-bit constant. For cost-modeling purposes, SelectInt64Count
+// Select a 64-bit constant. For cost-modeling purposes, getInt64Count
// (above) needs to be kept in sync with this function.
-static SDNode *SelectInt64Direct(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
+static SDNode *getInt64Direct(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
// Assume no remaining bits.
unsigned Remainder = 0;
// Assume no shift required.
@@ -754,10 +756,10 @@ static SDNode *SelectInt64Direct(Selecti
return Result;
}
-static SDNode *SelectInt64(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
- unsigned Count = SelectInt64CountDirect(Imm);
+static SDNode *getInt64(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
+ unsigned Count = getInt64CountDirect(Imm);
if (Count == 1)
- return SelectInt64Direct(CurDAG, dl, Imm);
+ return getInt64Direct(CurDAG, dl, Imm);
unsigned RMin = 0;
@@ -766,7 +768,7 @@ static SDNode *SelectInt64(SelectionDAG
for (unsigned r = 1; r < 63; ++r) {
uint64_t RImm = Rot64(Imm, r);
- unsigned RCount = SelectInt64CountDirect(RImm) + 1;
+ unsigned RCount = getInt64CountDirect(RImm) + 1;
if (RCount < Count) {
Count = RCount;
RMin = r;
@@ -789,7 +791,7 @@ static SDNode *SelectInt64(SelectionDAG
uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
uint64_t RImmWithOnes = RImm | OnesMask;
- RCount = SelectInt64CountDirect(RImmWithOnes) + 1;
+ RCount = getInt64CountDirect(RImmWithOnes) + 1;
if (RCount < Count) {
Count = RCount;
RMin = r;
@@ -799,24 +801,24 @@ static SDNode *SelectInt64(SelectionDAG
}
if (!RMin)
- return SelectInt64Direct(CurDAG, dl, Imm);
+ return getInt64Direct(CurDAG, dl, Imm);
auto getI32Imm = [CurDAG, dl](unsigned Imm) {
return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
};
- SDValue Val = SDValue(SelectInt64Direct(CurDAG, dl, MatImm), 0);
+ SDValue Val = SDValue(getInt64Direct(CurDAG, dl, MatImm), 0);
return CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Val,
getI32Imm(64 - RMin), getI32Imm(MaskEnd));
}
// Select a 64-bit constant.
-static SDNode *SelectInt64(SelectionDAG *CurDAG, SDNode *N) {
+static SDNode *getInt64(SelectionDAG *CurDAG, SDNode *N) {
SDLoc dl(N);
// Get 64 bit value.
int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
- return SelectInt64(CurDAG, dl, Imm);
+ return getInt64(CurDAG, dl, Imm);
}
namespace {
@@ -1646,7 +1648,7 @@ class BitPermutationSelector {
NumAndInsts += (unsigned) (ANDIMask != 0) + (unsigned) (ANDISMask != 0) +
(unsigned) (ANDIMask != 0 && ANDISMask != 0);
else
- NumAndInsts += SelectInt64Count(Mask) + /* and */ 1;
+ NumAndInsts += getInt64Count(Mask) + /* and */ 1;
unsigned NumRLInsts = 0;
bool FirstBG = true;
@@ -1709,7 +1711,7 @@ class BitPermutationSelector {
TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
ANDIVal, ANDISVal), 0);
} else {
- TotalVal = SDValue(SelectInt64(CurDAG, dl, Mask), 0);
+ TotalVal = SDValue(getInt64(CurDAG, dl, Mask), 0);
TotalVal =
SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
VRot, TotalVal), 0);
@@ -1852,9 +1854,9 @@ class BitPermutationSelector {
Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
ANDIVal, ANDISVal), 0);
} else {
- if (InstCnt) *InstCnt += SelectInt64Count(Mask) + /* and */ 1;
+ if (InstCnt) *InstCnt += getInt64Count(Mask) + /* and */ 1;
- SDValue MaskVal = SDValue(SelectInt64(CurDAG, dl, Mask), 0);
+ SDValue MaskVal = SDValue(getInt64(CurDAG, dl, Mask), 0);
Res =
SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
Res, MaskVal), 0);
@@ -1955,13 +1957,13 @@ public:
};
} // anonymous namespace
-SDNode *PPCDAGToDAGISel::SelectBitPermutation(SDNode *N) {
+bool PPCDAGToDAGISel::tryBitPermutation(SDNode *N) {
if (N->getValueType(0) != MVT::i32 &&
N->getValueType(0) != MVT::i64)
- return nullptr;
+ return false;
if (!UseBitPermRewriter)
- return nullptr;
+ return false;
switch (N->getOpcode()) {
default: break;
@@ -1971,11 +1973,15 @@ SDNode *PPCDAGToDAGISel::SelectBitPermut
case ISD::AND:
case ISD::OR: {
BitPermutationSelector BPS(CurDAG);
- return BPS.Select(N);
+ if (SDNode *New = BPS.Select(N)) {
+ ReplaceNode(N, New);
+ return true;
+ }
+ return false;
}
}
- return nullptr;
+ return false;
}
/// SelectCC - Select a comparison of the specified values with the specified
@@ -2255,7 +2261,7 @@ static unsigned int getVCmpInst(MVT VecV
}
}
-SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
+bool PPCDAGToDAGISel::trySETCC(SDNode *N) {
SDLoc dl(N);
unsigned Imm;
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
@@ -2276,20 +2282,22 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDN
Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
SDValue Ops[] = { Op, getI32Imm(27, dl), getI32Imm(5, dl),
getI32Imm(31, dl) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ return true;
}
case ISD::SETNE: {
if (isPPC64) break;
SDValue AD =
SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
Op, getI32Imm(~0U, dl)), 0);
- return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
- AD.getValue(1));
+ CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
+ return true;
}
case ISD::SETLT: {
SDValue Ops[] = { Op, getI32Imm(1, dl), getI32Imm(31, dl),
getI32Imm(31, dl) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ return true;
}
case ISD::SETGT: {
SDValue T =
@@ -2297,7 +2305,8 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDN
T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
SDValue Ops[] = { T, getI32Imm(1, dl), getI32Imm(31, dl),
getI32Imm(31, dl) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ return true;
}
}
} else if (Imm == ~0U) { // setcc op, -1
@@ -2308,18 +2317,20 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDN
if (isPPC64) break;
Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
Op, getI32Imm(1, dl)), 0);
- return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
- SDValue(CurDAG->getMachineNode(PPC::LI, dl,
- MVT::i32,
- getI32Imm(0, dl)),
- 0), Op.getValue(1));
+ CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
+ SDValue(CurDAG->getMachineNode(PPC::LI, dl,
+ MVT::i32,
+ getI32Imm(0, dl)),
+ 0), Op.getValue(1));
+ return true;
case ISD::SETNE: {
if (isPPC64) break;
Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
Op, getI32Imm(~0U, dl));
- return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
- Op, SDValue(AD, 1));
+ CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), Op,
+ SDValue(AD, 1));
+ return true;
}
case ISD::SETLT: {
SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
@@ -2328,14 +2339,15 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDN
Op), 0);
SDValue Ops[] = { AN, getI32Imm(1, dl), getI32Imm(31, dl),
getI32Imm(31, dl) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ return true;
}
case ISD::SETGT: {
SDValue Ops[] = { Op, getI32Imm(1, dl), getI32Imm(31, dl),
getI32Imm(31, dl) };
Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
- return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
- getI32Imm(1, dl));
+ CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1, dl));
+ return true;
}
}
}
@@ -2348,7 +2360,7 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDN
// vector compare operations return the same type as the operands.
if (LHS.getValueType().isVector()) {
if (PPCSubTarget->hasQPX())
- return nullptr;
+ return false;
EVT VecVT = LHS.getValueType();
bool Swap, Negate;
@@ -2360,16 +2372,17 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDN
EVT ResVT = VecVT.changeVectorElementTypeToInteger();
if (Negate) {
SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0);
- return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR :
- PPC::VNOR,
- ResVT, VCmp, VCmp);
+ CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR : PPC::VNOR,
+ ResVT, VCmp, VCmp);
+ return true;
}
- return CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS);
+ CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS);
+ return true;
}
if (PPCSubTarget->useCRBits())
- return nullptr;
+ return false;
bool Inv;
unsigned Idx = getCRIdxForSetCC(CC, Inv);
@@ -2388,31 +2401,33 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDN
SDValue Ops[] = { IntCR, getI32Imm((32 - (3 - Idx)) & 31, dl),
getI32Imm(31, dl), getI32Imm(31, dl) };
- if (!Inv)
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ if (!Inv) {
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ return true;
+ }
// Get the specified bit.
SDValue Tmp =
SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
- return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1, dl));
+ CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1, dl));
+ return true;
}
-SDNode *PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
+void PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
// Transfer memoperands.
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
- return Result;
}
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
-SDNode *PPCDAGToDAGISel::SelectImpl(SDNode *N) {
+void PPCDAGToDAGISel::Select(SDNode *N) {
SDLoc dl(N);
if (N->isMachineOpcode()) {
N->setNodeId(-1);
- return nullptr; // Already selected.
+ return; // Already selected.
}
// In case any misguided DAG-level optimizations form an ADD with a
@@ -2423,39 +2438,44 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
llvm_unreachable("Invalid ADD with TargetConstant operand");
// Try matching complex bit permutations before doing anything else.
- if (SDNode *NN = SelectBitPermutation(N))
- return NN;
+ if (tryBitPermutation(N))
+ return;
switch (N->getOpcode()) {
default: break;
case ISD::Constant: {
- if (N->getValueType(0) == MVT::i64)
- return SelectInt64(CurDAG, N);
+ if (N->getValueType(0) == MVT::i64) {
+ ReplaceNode(N, getInt64(CurDAG, N));
+ return;
+ }
break;
}
case ISD::SETCC: {
- SDNode *SN = SelectSETCC(N);
- if (SN)
- return SN;
+ if (trySETCC(N))
+ return;
break;
}
case PPCISD::GlobalBaseReg:
- return getGlobalBaseReg();
+ ReplaceNode(N, getGlobalBaseReg());
+ return;
case ISD::FrameIndex:
- return getFrameIndex(N, N);
+ selectFrameIndex(N, N);
+ return;
case PPCISD::MFOCRF: {
SDValue InFlag = N->getOperand(1);
- return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
- N->getOperand(0), InFlag);
+ ReplaceNode(N, CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
+ N->getOperand(0), InFlag));
+ return;
}
case PPCISD::READ_TIME_BASE: {
- return CurDAG->getMachineNode(PPC::ReadTB, dl, MVT::i32, MVT::i32,
- MVT::Other, N->getOperand(0));
+ ReplaceNode(N, CurDAG->getMachineNode(PPC::ReadTB, dl, MVT::i32, MVT::i32,
+ MVT::Other, N->getOperand(0)));
+ return;
}
case PPCISD::SRA_ADDZE: {
@@ -2468,16 +2488,18 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDNode *Op =
CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, MVT::Glue,
N0, ShiftAmt);
- return CurDAG->SelectNodeTo(N, PPC::ADDZE8, MVT::i64,
- SDValue(Op, 0), SDValue(Op, 1));
+ CurDAG->SelectNodeTo(N, PPC::ADDZE8, MVT::i64, SDValue(Op, 0),
+ SDValue(Op, 1));
+ return;
} else {
assert(N->getValueType(0) == MVT::i32 &&
"Expecting i64 or i32 in PPCISD::SRA_ADDZE");
SDNode *Op =
CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
N0, ShiftAmt);
- return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
- SDValue(Op, 0), SDValue(Op, 1));
+ CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, SDValue(Op, 0),
+ SDValue(Op, 1));
+ return;
}
}
@@ -2524,11 +2546,12 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr();
SDValue Ops[] = { Offset, Base, Chain };
- return transferMemOperands(
- N, CurDAG->getMachineNode(
- Opcode, dl, LD->getValueType(0),
- PPCLowering->getPointerTy(CurDAG->getDataLayout()), MVT::Other,
- Ops));
+ SDNode *MN = CurDAG->getMachineNode(
+ Opcode, dl, LD->getValueType(0),
+ PPCLowering->getPointerTy(CurDAG->getDataLayout()), MVT::Other, Ops);
+ transferMemOperands(N, MN);
+ ReplaceNode(N, MN);
+ return;
} else {
unsigned Opcode;
bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
@@ -2563,11 +2586,12 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr();
SDValue Ops[] = { Base, Offset, Chain };
- return transferMemOperands(
- N, CurDAG->getMachineNode(
- Opcode, dl, LD->getValueType(0),
- PPCLowering->getPointerTy(CurDAG->getDataLayout()), MVT::Other,
- Ops));
+ SDNode *MN = CurDAG->getMachineNode(
+ Opcode, dl, LD->getValueType(0),
+ PPCLowering->getPointerTy(CurDAG->getDataLayout()), MVT::Other, Ops);
+ transferMemOperands(N, MN);
+ ReplaceNode(N, MN);
+ return;
}
}
@@ -2582,7 +2606,8 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDValue Val = N->getOperand(0).getOperand(0);
SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl),
getI32Imm(ME, dl) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ return;
}
// If this is just a masked value where the input is not handled above, and
// is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
@@ -2592,7 +2617,8 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDValue Val = N->getOperand(0);
SDValue Ops[] = { Val, getI32Imm(0, dl), getI32Imm(MB, dl),
getI32Imm(ME, dl) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ return;
}
// If this is a 64-bit zero-extension mask, emit rldicl.
if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
@@ -2614,12 +2640,13 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
}
SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl) };
- return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
+ CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
+ return;
}
// AND X, 0 -> 0, not "rlwinm 32".
if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
ReplaceUses(SDValue(N, 0), N->getOperand(1));
- return nullptr;
+ return;
}
// ISD::OR doesn't get all the bitfield insertion fun.
// (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) might be a
@@ -2645,7 +2672,8 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
N->getOperand(0).getOperand(1),
getI32Imm(0, dl), getI32Imm(MB, dl),
getI32Imm(ME, dl) };
- return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
+ ReplaceNode(N, CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops));
+ return;
}
}
@@ -2654,8 +2682,8 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
}
case ISD::OR: {
if (N->getValueType(0) == MVT::i32)
- if (SDNode *I = SelectBitfieldInsert(N))
- return I;
+ if (tryBitfieldInsert(N))
+ return;
short Imm;
if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
@@ -2665,8 +2693,10 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
// If this is equivalent to an add, then we can fold it with the
// FrameIndex calculation.
- if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL)
- return getFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
+ if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) {
+ selectFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
+ return;
+ }
}
// Other cases are autogenerated.
@@ -2675,8 +2705,10 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
case ISD::ADD: {
short Imm;
if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
- isIntS16Immediate(N->getOperand(1), Imm))
- return getFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
+ isIntS16Immediate(N->getOperand(1), Imm)) {
+ selectFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
+ return;
+ }
break;
}
@@ -2687,7 +2719,8 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDValue Ops[] = { N->getOperand(0).getOperand(0),
getI32Imm(SH, dl), getI32Imm(MB, dl),
getI32Imm(ME, dl) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ return;
}
// Other cases are autogenerated.
@@ -2700,7 +2733,8 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDValue Ops[] = { N->getOperand(0).getOperand(0),
getI32Imm(SH, dl), getI32Imm(MB, dl),
getI32Imm(ME, dl) };
- return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
+ return;
}
// Other cases are autogenerated.
@@ -2726,9 +2760,9 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
PPC::sub_eq : PPC::sub_gt, dl, MVT::i32);
- return CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1,
- CR0Reg, SRIdxVal,
- SDValue(AndI.getNode(), 1) /* glue */);
+ CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1, CR0Reg,
+ SRIdxVal, SDValue(AndI.getNode(), 1) /* glue */);
+ return;
}
case ISD::SELECT_CC: {
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
@@ -2753,9 +2787,9 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDNode *Tmp =
CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
N->getOperand(0), getI32Imm(~0U, dl));
- return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
- SDValue(Tmp, 0), N->getOperand(0),
- SDValue(Tmp, 1));
+ CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(Tmp, 0),
+ N->getOperand(0), SDValue(Tmp, 1));
+ return;
}
SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
@@ -2786,7 +2820,8 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDValue NotCAndF(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
NotC, N->getOperand(3)), 0);
- return CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
+ CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
+ return;
}
unsigned BROpc = getPredicateForSetCC(CC);
@@ -2820,12 +2855,14 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
getI32Imm(BROpc, dl) };
- return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
+ CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
+ return;
}
case ISD::VSELECT:
if (PPCSubTarget->hasVSX()) {
SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
- return CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
+ CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
+ return;
}
break;
@@ -2856,8 +2893,8 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
SDValue Chain = LD->getChain();
SDValue Ops[] = { Base, Offset, Chain };
- return CurDAG->SelectNodeTo(N, PPC::LXVDSX,
- N->getValueType(0), Ops);
+ CurDAG->SelectNodeTo(N, PPC::LXVDSX, N->getValueType(0), Ops);
+ return;
}
}
@@ -2873,7 +2910,8 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), dl,
MVT::i32);
SDValue Ops[] = { Op1, Op2, DMV };
- return CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
+ CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
+ return;
}
break;
@@ -2881,10 +2919,11 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
case PPCISD::BDZ: {
bool IsPPC64 = PPCSubTarget->isPPC64();
SDValue Ops[] = { N->getOperand(1), N->getOperand(0) };
- return CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ ?
- (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
- (IsPPC64 ? PPC::BDZ8 : PPC::BDZ),
- MVT::Other, Ops);
+ CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ
+ ? (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
+ : (IsPPC64 ? PPC::BDZ8 : PPC::BDZ),
+ MVT::Other, Ops);
+ return;
}
case PPCISD::COND_BRANCH: {
// Op #0 is the Chain.
@@ -2900,7 +2939,8 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDValue Pred = getI32Imm(PCC, dl);
SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
N->getOperand(0), N->getOperand(4) };
- return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
+ CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
+ return;
}
case ISD::BR_CC: {
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
@@ -2922,8 +2962,9 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDValue BitComp(CurDAG->getMachineNode(Opc, dl, MVT::i1,
N->getOperand(Swap ? 3 : 2),
N->getOperand(Swap ? 2 : 3)), 0);
- return CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other,
- BitComp, N->getOperand(4), N->getOperand(0));
+ CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other, BitComp, N->getOperand(4),
+ N->getOperand(0));
+ return;
}
if (EnableBranchHint)
@@ -2932,7 +2973,8 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
SDValue Ops[] = { getI32Imm(PCC, dl), CondCode,
N->getOperand(4), N->getOperand(0) };
- return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
+ CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
+ return;
}
case ISD::BRIND: {
// FIXME: Should custom lower this.
@@ -2942,15 +2984,19 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
Chain), 0);
- return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
+ CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
+ return;
}
case PPCISD::TOC_ENTRY: {
assert ((PPCSubTarget->isPPC64() || PPCSubTarget->isSVR4ABI()) &&
"Only supported for 64-bit ABI and 32-bit SVR4");
if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {
SDValue GA = N->getOperand(0);
- return transferMemOperands(N, CurDAG->getMachineNode(PPC::LWZtoc, dl,
- MVT::i32, GA, N->getOperand(1)));
+ SDNode *MN = CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,
+ N->getOperand(1));
+ transferMemOperands(N, MN);
+ ReplaceNode(N, MN);
+ return;
}
// For medium and large code model, we generate two instructions as
@@ -2971,29 +3017,38 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
TOCbase, GA);
if (isa<JumpTableSDNode>(GA) || isa<BlockAddressSDNode>(GA) ||
- CModel == CodeModel::Large)
- return transferMemOperands(N, CurDAG->getMachineNode(PPC::LDtocL, dl,
- MVT::i64, GA, SDValue(Tmp, 0)));
+ CModel == CodeModel::Large) {
+ SDNode *MN = CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
+ SDValue(Tmp, 0));
+ transferMemOperands(N, MN);
+ ReplaceNode(N, MN);
+ return;
+ }
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
const GlobalValue *GV = G->getGlobal();
unsigned char GVFlags = PPCSubTarget->classifyGlobalReference(GV);
if (GVFlags & PPCII::MO_NLP_FLAG) {
- return transferMemOperands(N, CurDAG->getMachineNode(PPC::LDtocL, dl,
- MVT::i64, GA, SDValue(Tmp, 0)));
+ SDNode *MN = CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
+ SDValue(Tmp, 0));
+ transferMemOperands(N, MN);
+ ReplaceNode(N, MN);
+ return;
}
}
- return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
- SDValue(Tmp, 0), GA);
+ ReplaceNode(N, CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
+ SDValue(Tmp, 0), GA));
+ return;
}
case PPCISD::PPC32_PICGOT: {
// Generate a PIC-safe GOT reference.
assert(!PPCSubTarget->isPPC64() && PPCSubTarget->isSVR4ABI() &&
"PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
- return CurDAG->SelectNodeTo(
- N, PPC::PPC32PICGOT, PPCLowering->getPointerTy(CurDAG->getDataLayout()),
- MVT::i32);
+ CurDAG->SelectNodeTo(N, PPC::PPC32PICGOT,
+ PPCLowering->getPointerTy(CurDAG->getDataLayout()),
+ MVT::i32);
+ return;
}
case PPCISD::VADD_SPLAT: {
// This expands into one of three sequences, depending on whether
@@ -3035,7 +3090,8 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDValue EltVal = getI32Imm(Elt >> 1, dl);
SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
SDValue TmpVal = SDValue(Tmp, 0);
- return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal);
+ ReplaceNode(N, CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal));
+ return;
} else if (Elt > 0) {
// Elt is odd and positive, in the range [17,31].
@@ -3048,8 +3104,9 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
EltVal = getI32Imm(-16, dl);
SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
- return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
- SDValue(Tmp2, 0));
+ ReplaceNode(N, CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
+ SDValue(Tmp2, 0)));
+ return;
} else {
// Elt is odd and negative, in the range [-31,-17].
@@ -3062,13 +3119,14 @@ SDNode *PPCDAGToDAGISel::SelectImpl(SDNo
SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
EltVal = getI32Imm(-16, dl);
SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
- return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
- SDValue(Tmp2, 0));
+ ReplaceNode(N, CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
+ SDValue(Tmp2, 0)));
+ return;
}
}
}
- return SelectCode(N);
+ SelectCode(N);
}
// If the target supports the cmpb instruction, do the idiom recognition here.
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