[PATCH] D20310: Teach LLVM about Power 9 D-Form VSX Instructions

Chuang-Yu Cheng via llvm-commits llvm-commits at lists.llvm.org
Fri May 20 04:08:13 PDT 2016


cycheng added a comment.

In http://reviews.llvm.org/D20310#432000, @nemanjai wrote:

> This is going to need some additional work to restrict the register sets for all the instructions. Of course, these are scalar loads/stores but they're restricted to the upper 32 VSX registers (the VMX registers) so we can't use the full vsfrc/vssrc register classes.


I missed Nemanjai's comment, I did some test and looks like we can use vfrc register calss instead:

- assembler/dis-assembler:

  static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                              uint64_t Address,
                                              const void *Decoder) {
    return decodeRegisterClass(Inst, RegNo, VSFRegs);
  }
  
    void addRegVFRCOperands(MCInst &Inst, unsigned N) const {
      assert(N == 1 && "Invalid number of operands!");
      Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
    }



- PPCInstrVSX.td

  def PPCRegVFRCAsmOperand : AsmOperandClass {
    let Name = "RegVFRC"; let PredicateMethod = "isVSRegNumber";
  }
  def vfrc : RegisterOperand<VFRC> {
    let ParserMatchClass = PPCRegVFRCAsmOperand;
  }
  
    // Load DWord
    def LXSD  : DSForm_1<57, 2, (outs vfrc:$vD), (ins memrix:$src),
                         "lxsd $vD, $src", IIC_LdStLFD, []>;
    // Load SP from src, convert it to DP, and place in dword[0]
    def LXSSP : DSForm_1<57, 3, (outs vfrc:$vD), (ins memrix:$src),
                         "lxssp $vD, $src", IIC_LdStLFD, []>;
  
    // Store DWord
    def STXSD  : DSForm_1<61, 2, (outs), (ins vfrc:$vS, memrix:$dst),
                          "stxsd $vS, $dst", IIC_LdStSTFD, []>;
    // Convert DP of dword[0] to SP, and Store to dst
    def STXSSP : DSForm_1<61, 3, (outs), (ins vfrc:$vS, memrix:$dst),
                          "stxssp $vS, $dst", IIC_LdStSTFD, []>;
  
    let AddedComplexity = 500 in {
      def : Pat<(f64 (load iaddr:$src)), (LXSD  iaddr:$src)>;
      def : Pat<(f32 (load iaddr:$src)), (COPY_TO_REGCLASS (LXSSP iaddr:$src), VFRC)>;
      def : Pat<(f64 (extloadf32 iaddr:$src)),
              (COPY_TO_REGCLASS (LXSSP iaddr:$src), VFRC)>;
      def : Pat<(store f64:$vS, iaddr:$dst), (STXSD $vS, iaddr:$dst)>;
      def : Pat<(store f32:$vS, iaddr:$dst), (STXSSP (COPY_TO_REGCLASS $vS, VFRC), iaddr:$dst)>;
    }



- Test case result:

          lxsd 35, 8(3)
          lxsd 36, 16(3)
          lxsd 32, 24(3)
  ...


http://reviews.llvm.org/D20310





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