[llvm] r270057 - [ARM] Add cdp intrinsic tests.

[Ranjeet Singh via llvm-commits]

Author: rsingh
Date: Thu May 19 07:59:17 2016
New Revision: 270057

URL: http://llvm.org/viewvc/llvm-project?rev=270057&view=rev
Log:
[ARM] Add cdp intrinsic tests.

- Renamed intrinsics.ll to intrinsics-coprocessor.ll
  as all the tests were testing coprocessor instructions,
  also made the test checks match the full instruction.

Differential Revision: http://reviews.llvm.org/D20393


Added:
    llvm/trunk/test/CodeGen/ARM/cdp.ll
    llvm/trunk/test/CodeGen/ARM/cdp2.ll
    llvm/trunk/test/CodeGen/ARM/intrinsics-coprocessor.ll
Removed:
    llvm/trunk/test/CodeGen/ARM/intrinsics.ll

Added: llvm/trunk/test/CodeGen/ARM/cdp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/cdp.ll?rev=270057&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/cdp.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/cdp.ll Thu May 19 07:59:17 2016
@@ -0,0 +1,13 @@
+; RUN: not llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
+; RUN: not llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.cdp
+define void @cdp(i32 %a) #0 {
+  %a.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  %1 = load i32, i32* %a.addr, align 4
+  call void @llvm.arm.cdp(i32 %1, i32 2, i32 3, i32 4, i32 5, i32 6)
+  ret void
+}
+
+declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind

Added: llvm/trunk/test/CodeGen/ARM/cdp2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/cdp2.ll?rev=270057&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/cdp2.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/cdp2.ll Thu May 19 07:59:17 2016
@@ -0,0 +1,13 @@
+; RUN: not llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
+; RUN: not llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.cdp2
+define void @cdp2(i32 %a) #0 {
+  %a.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  %1 = load i32, i32* %a.addr, align 4
+  call void @llvm.arm.cdp2(i32 %1, i32 2, i32 3, i32 4, i32 5, i32 6)
+  ret void
+}
+
+declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind

Added: llvm/trunk/test/CodeGen/ARM/intrinsics-coprocessor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/intrinsics-coprocessor.ll?rev=270057&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/intrinsics-coprocessor.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/intrinsics-coprocessor.ll Thu May 19 07:59:17 2016
@@ -0,0 +1,39 @@
+; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s
+; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 | FileCheck %s
+
+define void @coproc() nounwind {
+entry:
+  ; CHECK: mrc p7, #1, r0, c1, c1, #4
+  %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
+  ; CHECK: mcr p7, #1, r0, c1, c1, #4
+  tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
+  ; CHECK: mrc2 p7, #1, r1, c1, c1, #4
+  %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
+  ; CHECK: mcr2 p7, #1, r1, c1, c1, #4
+  tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
+  ; CHECK: mcrr p7, #1, r0, r1, c1
+  tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
+  ; CHECK: mcrr2 p7, #1, r0, r1, c1
+  tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
+  ; CHECK: cdp p7, #3, c1, c1, c1, #5
+  tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
+  ; CHECK: cdp2 p7, #3, c1, c1, c1, #5
+  tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
+  ret void
+}
+
+declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind
+
+declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind
+
+declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind
+
+declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind
+
+declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind
+
+declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind
+
+declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind
+
+declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind

Removed: llvm/trunk/test/CodeGen/ARM/intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/intrinsics.ll?rev=270056&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/intrinsics.ll (removed)
@@ -1,39 +0,0 @@
-; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s
-; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 | FileCheck %s
-
-define void @coproc() nounwind {
-entry:
-  ; CHECK: mrc
-  %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
-  ; CHECK: mcr
-  tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
-  ; CHECK: mrc2
-  %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
-  ; CHECK: mcr2
-  tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
-  ; CHECK: mcrr
-  tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
-  ; CHECK: mcrr2
-  tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
-  ; CHECK: cdp
-  tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
-  ; CHECK: cdp2
-  tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
-  ret void
-}
-
-declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind
-
-declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind
-
-declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind
-
-declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind
-
-declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind
-
-declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind
-
-declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind
-
-declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind