[llvm] r270002 - AMDGPU: Fix verifier error when spilling undef subreg
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed May 18 16:35:55 PDT 2016
Author: arsenm
Date: Wed May 18 18:35:53 2016
New Revision: 270002
URL: http://llvm.org/viewvc/llvm-project?rev=270002&view=rev
Log:
AMDGPU: Fix verifier error when spilling undef subreg
Modified:
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=270002&r1=270001&r2=270002&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Wed May 18 18:35:53 2016
@@ -505,9 +505,11 @@ void SIRegisterInfo::eliminateFrameIndex
unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+ unsigned SuperReg = MI->getOperand(0).getReg();
for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
- unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
+ unsigned SubReg = getPhysRegSubReg(SuperReg,
&AMDGPU::SGPR_32RegClass, i);
+
struct SIMachineFunctionInfo::SpilledReg Spill =
MFI->getSpilledReg(MF, Index, i);
@@ -524,8 +526,14 @@ void SIRegisterInfo::eliminateFrameIndex
} else {
// Spill SGPR to a frame index.
// FIXME we should use S_STORE_DWORD here for VI.
- BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
- .addReg(SubReg);
+ MachineInstrBuilder Mov
+ = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
+ .addReg(SubReg);
+
+ // There could be undef components of a spilled super register.
+ // TODO: Can we detect this and skip the spill?
+ if (NumSubRegs > 1)
+ Mov.addReg(SuperReg, RegState::Implicit);
unsigned Size = FrameInfo->getObjectSize(Index);
unsigned Align = FrameInfo->getObjectAlignment(Index);
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