[llvm] r269963 - [AArch64] Minor refactoring. NFC.
Chad Rosier via llvm-commits
llvm-commits at lists.llvm.org
Wed May 18 10:43:12 PDT 2016
Author: mcrosier
Date: Wed May 18 12:43:11 2016
New Revision: 269963
URL: http://llvm.org/viewvc/llvm-project?rev=269963&view=rev
Log:
[AArch64] Minor refactoring. NFC.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp?rev=269963&r1=269962&r2=269963&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp Wed May 18 12:43:11 2016
@@ -1987,13 +1987,12 @@ static bool tryBitfieldInsertOpFromOr(SD
SelectionDAG *CurDAG) {
assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
- SDValue Dst, Src;
- unsigned ImmR, ImmS;
-
EVT VT = N->getValueType(0);
if (VT != MVT::i32 && VT != MVT::i64)
return false;
+ unsigned BitWidth = VT.getSizeInBits();
+
// Because of simplify-demanded-bits in DAGCombine, involved masks may not
// have the expected shape. Try to undo that.
@@ -2011,6 +2010,8 @@ static bool tryBitfieldInsertOpFromOr(SD
// and/or inserting fewer extra instructions.
for (int I = 0; I < 4; ++I) {
+ SDValue Dst, Src;
+ unsigned ImmR, ImmS;
bool BiggerPattern = I / 2;
SDNode *OrOpd0 = N->getOperand(I % 2).getNode();
SDValue OrOpd1Val = N->getOperand((I + 1) % 2);
@@ -2040,7 +2041,7 @@ static bool tryBitfieldInsertOpFromOr(SD
} else if (isBitfieldPositioningOp(CurDAG, SDValue(OrOpd0, 0),
BiggerPattern,
Src, DstLSB, Width)) {
- ImmR = (VT.getSizeInBits() - DstLSB) % VT.getSizeInBits();
+ ImmR = (BitWidth - DstLSB) % BitWidth;
ImmS = Width - 1;
} else
continue;
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