[llvm] r269897 - Revert "[mips] Restrict the creation of compact branches"

[Simon Dardis via llvm-commits]

Author: sdardis
Date: Wed May 18 04:51:37 2016
New Revision: 269897

URL: http://llvm.org/viewvc/llvm-project?rev=269897&view=rev
Log:
Revert "[mips] Restrict the creation of compact branches"

This reverts commit rL269893.

Incorrect patch applied.

Modified:
    llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
    llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
    llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp

Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp?rev=269897&r1=269896&r2=269897&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp Wed May 18 04:51:37 2016
@@ -106,26 +106,6 @@ static void LowerDins(MCInst& InstIn) {
   return;
 }
 
-// Fix a bad compact branch encoding for beqc/bnec.
-void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
-
-  // Encoding may be illegal !(rs < rt), but this situation is
-  // easily fixed.
-  unsigned RegOp0 = Inst.getOperand(0).getReg();
-  unsigned RegOp1 = Inst.getOperand(1).getReg();
-
-  unsigned Reg0 =  Ctx.getRegisterInfo()->getEncodingValue(RegOp0);
-  unsigned Reg1 =  Ctx.getRegisterInfo()->getEncodingValue(RegOp1);
-
-  assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!");
-  if (Reg0 < Reg1)
-    return;
-
-  Inst.getOperand(0).setReg(RegOp1);
-  Inst.getOperand(1).setReg(RegOp0);
-
-}
-
 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
   return STI.getFeatureBits()[Mips::FeatureMicroMips];
 }
@@ -180,11 +160,6 @@ encodeInstruction(const MCInst &MI, raw_
     // Double extract instruction is chosen by pos and size operands
   case Mips::DINS:
     LowerDins(TmpInst);
-    break;
-  // Compact branches.
-  case Mips::BEQC:
-  case Mips::BNEC:
-    LowerCompactBranch(TmpInst);
   }
 
   unsigned long N = Fixups.size();

Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h?rev=269897&r1=269896&r2=269897&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h Wed May 18 04:51:37 2016
@@ -253,8 +253,6 @@ public:
   unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
                                     SmallVectorImpl<MCFixup> &Fixups,
                                     const MCSubtargetInfo &STI) const;
-  private:
-  void LowerCompactBranch(MCInst& Inst) const;
 }; // class MipsMCCodeEmitter
 } // namespace llvm.
 

Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td?rev=269897&r1=269896&r2=269897&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td Wed May 18 04:51:37 2016
@@ -360,7 +360,7 @@ class SPECIAL_SDBBP_FM : MipsR6Inst {
 }
 
 // This class is ambiguous with other branches:
-//   BEQC/BNEC require that rs < rt
+//   BEQC/BNEC require that rs > rt
 class CMP_BRANCH_2R_OFF16_FM<OPGROUP funct> : MipsR6Inst {
   bits<5> rs;
   bits<5> rt;

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=269897&r1=269896&r2=269897&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Wed May 18 04:51:37 2016
@@ -282,16 +282,6 @@ unsigned MipsInstrInfo::getEquivalentCom
     }
   }
 
-  // MIPSR6 forbids both operands being the zero register.
-  if (Subtarget.hasMips32r6() &&
-      (I->getOperand(0).getType() == MachineOperand::MO_Register &&
-       (I->getOperand(0).getReg() == Mips::ZERO ||
-        I->getOperand(0).getReg() == Mips::ZERO_64)) &&
-      (I->getOperand(1).getType() == MachineOperand::MO_Register &&
-       (I->getOperand(1).getReg() == Mips::ZERO ||
-        I->getOperand(1).getReg() == Mips::ZERO_64)))
-    return 0;
-
   if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
     switch (Opcode) {
     case Mips::B:
@@ -309,12 +299,8 @@ unsigned MipsInstrInfo::getEquivalentCom
       else
         return Mips::BNEC;
     case Mips::BGE:
-      if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
-        return 0;
       return Mips::BGEC;
     case Mips::BGEU:
-      if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
-        return 0;
       return Mips::BGEUC;
     case Mips::BGEZ:
       return Mips::BGEZC;
@@ -323,12 +309,8 @@ unsigned MipsInstrInfo::getEquivalentCom
     case Mips::BLEZ:
       return Mips::BLEZC;
     case Mips::BLT:
-      if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
-        return 0;
       return Mips::BLTC;
     case Mips::BLTU:
-      if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
-        return 0;
       return Mips::BLTUC;
     case Mips::BLTZ:
       return Mips::BLTZC;
@@ -348,7 +330,7 @@ unsigned MipsInstrInfo::getEquivalentCom
       return Mips::JIC64;
     case Mips::JALR64Pseudo:
       return Mips::JIALC64;
-    default:
+     default:
       return 0;
     }
   }