[PATCH] D20185: [AArch64] Fix bug in large stack spill slot handling (PR27717)

[Geoff Berry via llvm-commits]

gberry added a comment.

I spent some time trying to come up with a smaller test case without much luck.  The problem is you need to generate enough spill code that the spill slot address offset doesn't fit in the load/store offset field, and have all GPRs live at the point where the too large spill offset occurs.  I couldn't come up with a way to do that, though perhaps others have some idea here.

I could add the original test case, but it seems like it would be fairly fragile in that later changes in register allocation, etc. could easily make it no longer test what it was intended to test.


http://reviews.llvm.org/D20185