[llvm] r269664 - [Hexagon] Simplify HexagonInstrInfo::isPredicable

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Mon May 16 11:56:10 2016
New Revision: 269664

URL: http://llvm.org/viewvc/llvm-project?rev=269664&view=rev
Log:
[Hexagon] Simplify HexagonInstrInfo::isPredicable

Remove all the checks for constant extenders from isPredicable. The users
of it should be the ones checking cost/profitability.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
    llvm/trunk/test/CodeGen/Hexagon/cext-check.ll

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=269664&r1=269663&r2=269664&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Mon May 16 11:56:10 2016
@@ -1254,6 +1254,7 @@ bool HexagonInstrInfo::isPredicated(cons
   return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
 }
 
+
 bool HexagonInstrInfo::PredicateInstruction(
     MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
   if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
@@ -1312,6 +1313,7 @@ bool HexagonInstrInfo::SubsumesPredicate
   return false;
 }
 
+
 bool HexagonInstrInfo::DefinesPredicate(
     MachineInstr &MI, std::vector<MachineOperand> &Pred) const {
   auto &HRI = getRegisterInfo();
@@ -1328,91 +1330,9 @@ bool HexagonInstrInfo::DefinesPredicate(
   return false;
 }
 
-bool HexagonInstrInfo::isPredicable(MachineInstr &MI) const {
-  bool isPred = MI.getDesc().isPredicable();
-
-  if (!isPred)
-    return false;
-
-  const int Opc = MI.getOpcode();
-  int NumOperands = MI.getNumOperands();
-
-  // Keep a flag for upto 4 operands in the instructions, to indicate if
-  // that operand has been constant extended.
-  bool OpCExtended[4] = {false};
-  if (NumOperands > 4)
-    NumOperands = 4;
-
-  for (int i = 0; i < NumOperands; i++)
-    OpCExtended[i] = (isOperandExtended(&MI, i) && isConstExtended(&MI));
-
-  switch(Opc) {
-  case Hexagon::A2_tfrsi:
-    return (isOperandExtended(&MI, 1) && isConstExtended(&MI)) ||
-           isInt<12>(MI.getOperand(1).getImm());
-
-  case Hexagon::S2_storerd_io:
-    return isShiftedUInt<6,3>(MI.getOperand(1).getImm());
-
-  case Hexagon::S2_storeri_io:
-  case Hexagon::S2_storerinew_io:
-    return isShiftedUInt<6,2>(MI.getOperand(1).getImm());
-
-  case Hexagon::S2_storerh_io:
-  case Hexagon::S2_storerhnew_io:
-    return isShiftedUInt<6,1>(MI.getOperand(1).getImm());
-
-  case Hexagon::S2_storerb_io:
-  case Hexagon::S2_storerbnew_io:
-    return isUInt<6>(MI.getOperand(1).getImm());
-
-  case Hexagon::L2_loadrd_io:
-    return isShiftedUInt<6,3>(MI.getOperand(2).getImm());
-
-  case Hexagon::L2_loadri_io:
-    return isShiftedUInt<6,2>(MI.getOperand(2).getImm());
 
-  case Hexagon::L2_loadrh_io:
-  case Hexagon::L2_loadruh_io:
-    return isShiftedUInt<6,1>(MI.getOperand(2).getImm());
-
-  case Hexagon::L2_loadrb_io:
-  case Hexagon::L2_loadrub_io:
-    return isUInt<6>(MI.getOperand(2).getImm());
-
-  case Hexagon::L2_loadrd_pi:
-    return isShiftedInt<4,3>(MI.getOperand(3).getImm());
-
-  case Hexagon::L2_loadri_pi:
-    return isShiftedInt<4,2>(MI.getOperand(3).getImm());
-
-  case Hexagon::L2_loadrh_pi:
-  case Hexagon::L2_loadruh_pi:
-    return isShiftedInt<4,1>(MI.getOperand(3).getImm());
-
-  case Hexagon::L2_loadrb_pi:
-  case Hexagon::L2_loadrub_pi:
-    return isInt<4>(MI.getOperand(3).getImm());
-
-  case Hexagon::S4_storeirb_io:
-  case Hexagon::S4_storeirh_io:
-  case Hexagon::S4_storeiri_io:
-    return (OpCExtended[1] || isUInt<6>(MI.getOperand(1).getImm())) &&
-           (OpCExtended[2] || isInt<6>(MI.getOperand(2).getImm()));
-
-  case Hexagon::A2_addi:
-    return isInt<8>(MI.getOperand(2).getImm());
-
-  case Hexagon::A2_aslh:
-  case Hexagon::A2_asrh:
-  case Hexagon::A2_sxtb:
-  case Hexagon::A2_sxth:
-  case Hexagon::A2_zxtb:
-  case Hexagon::A2_zxth:
-    return true;
-  }
-
-  return true;
+bool HexagonInstrInfo::isPredicable(MachineInstr &MI) const {
+  return MI.getDesc().isPredicable();
 }
 
 
@@ -3497,6 +3417,7 @@ int HexagonInstrInfo::getDotNewOp(const
   return 0;
 }
 
+
 // Returns the opcode to use when converting MI, which is a conditional jump,
 // into a conditional instruction which uses the .new value of the predicate.
 // We also use branch probabilities to add a hint to the jump.

Modified: llvm/trunk/test/CodeGen/Hexagon/cext-check.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cext-check.ll?rev=269664&r1=269663&r2=269664&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/cext-check.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/cext-check.ll Mon May 16 11:56:10 2016
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon -hexagon-eif=0 -ifcvt-limit=0 < %s | FileCheck %s
 ; Check that we constant extended instructions only when necessary.
 
 define i32 @cext_test1(i32* %a) nounwind {