[PATCH] D20284: [mips] Restrict the creation of compact branches

[Daniel Sanders via llvm-commits]

dsanders accepted this revision.
dsanders added a comment.
This revision is now accepted and ready to land.

LGTM with a couple nits


================
Comment at: lib/Target/Mips/Mips32r6InstrFormats.td:363
@@ -362,3 +362,3 @@
 // This class is ambiguous with other branches:
-//   BEQC/BNEC require that rs > rt
+//   BEQC/BNEC require that rs < rt
 class CMP_BRANCH_2R_OFF16_FM<OPGROUP funct> : MipsR6Inst {
----------------
&& rs != 0

We can also say '&& rt != 0' if we want but the 'rs < rt' already covers it.

================
Comment at: lib/Target/Mips/MipsInstrInfo.cpp:286-292
@@ +285,9 @@
+  // MIPSR6 forbids both operands being the zero register.
+  if (Subtarget.hasMips32r6() &&
+      (I->getOperand(0).getType() == MachineOperand::MO_Register &&
+       (I->getOperand(0).getReg() == Mips::ZERO ||
+        I->getOperand(0).getReg() == Mips::ZERO_64)) &&
+      (I->getOperand(1).getType() == MachineOperand::MO_Register &&
+       (I->getOperand(1).getReg() == Mips::ZERO ||
+        I->getOperand(1).getReg() == Mips::ZERO_64)))
+    return 0;
----------------
We can use MachineOperand::isReg() instead of the getType() checks.
We should check the number of operands since some instructions have one (e.g. B, PseudoReturn) or zero operands.



Repository:
  rL LLVM

http://reviews.llvm.org/D20284