[PATCH] D16719: [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions

Simon Dardis via llvm-commits llvm-commits at lists.llvm.org
Mon May 16 05:19:20 PDT 2016


sdardis requested changes to this revision.
sdardis added a comment.
This revision now requires changes to proceed.

Some nits and a question as to why llvm is generating 2 instructions instead of 1.


================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:605
@@ -605,1 +604,3 @@
+class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>;
 class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd>;
+class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>;
----------------
Requires AddedComplexity = 1.

================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:1007
@@ -1004,3 +1006,3 @@
       MMR6Arch<"andi16">;
 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
----------------
Also requires AddedComplexity = 1

================
Comment at: lib/Target/Mips/MicroMipsInstrInfo.td:1052
@@ -1048,3 +1051,3 @@
 
 def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
 
----------------
This needs to be covered with "let Predicates = [InMicroMips] in {"

================
Comment at: test/CodeGen/Mips/llvm-ir/or.ll:173-174
@@ +172,4 @@
+
+  ; MMR6:         li16    $2, 4
+  ; MMR6:         or16    $2, $4
+
----------------
Why is LLVM generating two instructions here rather than a single long form 'or'? Similarly for xor.

================
Comment at: test/MC/Disassembler/Mips/micromips32r3/valid-el.txt:197
@@ +196,2 @@
+0x64 0x70 0x05 0x00 # CHECK: xori $3, $4, 5
+0x04 0x00 0xd0 0x1a # CHECK: not $3, $4
----------------
This requires not16 and nor. The 32bit andi, ori, xori, not are not required as they already exist in this file.

================
Comment at: test/MC/Disassembler/Mips/micromips32r3/valid.txt:197
@@ +196,2 @@
+0x70 0x64 0x00 0x05 # CHECK: xori $3, $4, 5
+0x00 0x04 0x1a 0xd0 # CHECK: not $3, $4
----------------
See my above comment.

================
Comment at: test/MC/Disassembler/Mips/micromips32r6/valid.txt:315
@@ +314,2 @@
+0x70 0x64 0x00 0x05 # CHECK: xori $3, $4, 5
+0x00 0x04 0x1a 0xd0 # CHECK: not $3, $4
----------------
andi, ori, xori are already exist in this file, so there's no need to duplicate them.

================
Comment at: test/MC/Mips/micromips-alu-instructions.s:132
@@ -115,1 +131,3 @@
     addiupc $7, -16777216
+    and    $3, $4, 5
+    and    $3, 5
----------------
Already covered by and $9, $6, 17767

================
Comment at: test/MC/Mips/micromips-alu-instructions.s:136
@@ +135,3 @@
+    or     $3, 5
+    xor    $3, $4, 5
+    xor    $3, 5
----------------
Already covered by xor $9, $6, 17767

================
Comment at: test/MC/Mips/micromips64r6/valid.s:15
@@ -13,2 +14,3 @@
+        andi16 $4, $5, 8         # CHECK: andi16 $4, $5, 8    # encoding: [0x2e,0x56]
         b 132                    # CHECK: bc16 132            # encoding: [0xcc,0x42]
         bc16 132                 # CHECK: bc16 132            # encoding: [0xcc,0x42]
----------------
This also needs to check not16.


http://reviews.llvm.org/D16719





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