[llvm] r269615 - [X86][SSE] Simplify zero'th index extract element matching

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sun May 15 15:22:50 2016
New Revision: 269615

URL: http://llvm.org/viewvc/llvm-project?rev=269615&view=rev
Log:
[X86][SSE] Simplify zero'th index extract element matching

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=269615&r1=269614&r2=269615&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun May 15 15:22:50 2016
@@ -12235,10 +12235,11 @@ X86TargetLowering::LowerEXTRACT_VECTOR_E
   MVT VT = Op.getSimpleValueType();
   // TODO: handle v16i8.
   if (VT.getSizeInBits() == 16) {
-    if (isNullConstant(Idx))
+    if (IdxVal == 0)
       return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
                          DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
                                      DAG.getBitcast(MVT::v4i32, Vec), Idx));
+
     // Transform it so it match pextrw which produces a 32-bit result.
     MVT EltVT = MVT::i32;
     SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, Vec, Idx);
@@ -12262,7 +12263,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_E
     // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
     // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
     //        to match extract_elt for f64.
-    if (isNullConstant(Idx))
+    if (IdxVal == 0)
       return Op;
 
     // UNPCKHPD the element to the lowest double word, then movsd.