[llvm] r269512 - [AArch64] Simplify logic to reduce vertical space. NFC.

[Chad Rosier via llvm-commits]

Author: mcrosier
Date: Fri May 13 17:53:13 2016
New Revision: 269512

URL: http://llvm.org/viewvc/llvm-project?rev=269512&view=rev
Log:
[AArch64] Simplify logic to reduce vertical space. NFC.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp?rev=269512&r1=269511&r2=269512&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp Fri May 13 17:53:13 2016
@@ -2110,12 +2110,7 @@ bool AArch64DAGToDAGISel::tryBitfieldIns
     return false;
 
   EVT VT = N->getValueType(0);
-  unsigned Opc;
-  if (VT == MVT::i32)
-    Opc = AArch64::UBFMWri;
-  else if (VT == MVT::i64)
-    Opc = AArch64::UBFMXri;
-  else
+  if (VT != MVT::i32 && VT != MVT::i64)
     return false;
 
   SDValue Op0;
@@ -2132,6 +2127,7 @@ bool AArch64DAGToDAGISel::tryBitfieldIns
   SDLoc DL(N);
   SDValue Ops[] = {Op0, CurDAG->getTargetConstant(ImmR, DL, VT),
                    CurDAG->getTargetConstant(ImmS, DL, VT)};
+  unsigned Opc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
   CurDAG->SelectNodeTo(N, Opc, VT, Ops);
   return true;
 }