[llvm] r269478 - AMDGPU/R600: Add support for emitting MCExpr
Jan Vesely via llvm-commits
llvm-commits at lists.llvm.org
Fri May 13 13:39:26 PDT 2016
Author: jvesely
Date: Fri May 13 15:39:26 2016
New Revision: 269478
URL: http://llvm.org/viewvc/llvm-project?rev=269478&view=rev
Log:
AMDGPU/R600: Add support for emitting MCExpr
Reviewers: tstellard
Subscribers: arsenm
Differential Revision: http://reviews.llvm.org/D19791
Modified:
llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp?rev=269478&r1=269477&r2=269478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp Fri May 13 15:39:26 2016
@@ -73,12 +73,16 @@ void AMDGPUMCObjectWriter::writeObject(M
static unsigned getFixupKindNumBytes(unsigned Kind) {
switch (Kind) {
+ case FK_SecRel_1:
case FK_Data_1:
return 1;
+ case FK_SecRel_2:
case FK_Data_2:
return 2;
+ case FK_SecRel_4:
case FK_Data_4:
return 4;
+ case FK_SecRel_8:
case FK_Data_8:
return 8;
default:
Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp?rev=269478&r1=269477&r2=269478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp Fri May 13 15:39:26 2016
@@ -15,6 +15,7 @@
//===----------------------------------------------------------------------===//
#include "R600Defines.h"
+#include "MCTargetDesc/AMDGPUFixupKinds.h"
#include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/MC/MCCodeEmitter.h"
@@ -164,7 +165,7 @@ unsigned R600MCCodeEmitter::getHWReg(uns
uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
const MCOperand &MO,
- SmallVectorImpl<MCFixup> &Fixup,
+ SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MO.isReg()) {
if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
@@ -172,6 +173,19 @@ uint64_t R600MCCodeEmitter::getMachineOp
return getHWReg(MO.getReg());
}
+ if (MO.isExpr()) {
+ const MCSymbolRefExpr *Expr = cast<MCSymbolRefExpr>(MO.getExpr());
+ // We put rodata at the end of code section, then map the entire
+ // code secetion as vtx buf. Thus the section relative address is the
+ // correct one.
+ // Each R600 literal instruction has two operands
+ // We can't easily get the order of the current one, so compare against
+ // the first one and adjust offset.
+ const unsigned offset = (&MO == &MI.getOperand(0)) ? 0 : 4;
+ Fixups.push_back(MCFixup::create(offset, Expr, FK_SecRel_4, MI.getLoc()));
+ return 0;
+ }
+
assert(MO.isImm());
return MO.getImm();
}
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