[llvm] r269328 - [Hexagon] Expand VSelect pseudo instructions

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Thu May 12 14:16:02 2016
New Revision: 269328

URL: http://llvm.org/viewvc/llvm-project?rev=269328&view=rev
Log:
[Hexagon] Expand VSelect pseudo instructions

Added:
    llvm/trunk/test/CodeGen/Hexagon/vselect-pseudo.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=269328&r1=269327&r2=269328&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Thu May 12 14:16:02 2016
@@ -1152,6 +1152,44 @@ bool HexagonInstrInfo::expandPostRAPseud
       MBB.erase(MI);
       return true;
     }
+    case Hexagon::VSelectPseudo_V6: {
+      const MachineOperand &Op0 = MI->getOperand(0);
+      const MachineOperand &Op1 = MI->getOperand(1);
+      const MachineOperand &Op2 = MI->getOperand(2);
+      const MachineOperand &Op3 = MI->getOperand(3);
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
+        .addOperand(Op0)
+        .addOperand(Op1)
+        .addOperand(Op2);
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
+        .addOperand(Op0)
+        .addOperand(Op1)
+        .addOperand(Op3);
+      MBB.erase(MI);
+      return true;
+    }
+    case Hexagon::VSelectDblPseudo_V6: {
+      MachineOperand &Op0 = MI->getOperand(0);
+      MachineOperand &Op1 = MI->getOperand(1);
+      MachineOperand &Op2 = MI->getOperand(2);
+      MachineOperand &Op3 = MI->getOperand(3);
+      unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::subreg_loreg);
+      unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::subreg_hireg);
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
+        .addOperand(Op0)
+        .addOperand(Op1)
+        .addReg(SrcHi)
+        .addReg(SrcLo);
+      SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::subreg_loreg);
+      SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::subreg_hireg);
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
+        .addOperand(Op0)
+        .addOperand(Op1)
+        .addReg(SrcHi)
+        .addReg(SrcLo);
+      MBB.erase(MI);
+      return true;
+    }
     case Hexagon::TCRETURNi:
       MI->setDesc(get(Hexagon::J2_jump));
       return true;

Added: llvm/trunk/test/CodeGen/Hexagon/vselect-pseudo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/vselect-pseudo.ll?rev=269328&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/vselect-pseudo.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/vselect-pseudo.ll Thu May 12 14:16:02 2016
@@ -0,0 +1,33 @@
+; RUN: llc -march=hexagon < %s
+; REQUIRES: asserts
+
+target triple = "hexagon"
+
+; Function Attrs: nounwind
+define void @fred() #0 {
+entry:
+  br label %for.body9.us
+
+for.body9.us:
+  %cmp10.us = icmp eq i32 0, undef
+  %.h63h32.2.us = select i1 %cmp10.us, <16 x i32> zeroinitializer, <16 x i32> undef
+  %0 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %.h63h32.2.us, <16 x i32> undef, i32 2)
+  %1 = tail call <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1> undef, <16 x i32> undef, <16 x i32> %0)
+  %2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %1)
+  %3 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %2, i32 62)
+  %4 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %3)
+  store <16 x i32> %4, <16 x i32>* undef, align 64
+  br i1 undef, label %for.body9.us, label %for.body43.us.preheader
+
+for.body43.us.preheader:                          ; preds = %for.body9.us
+  ret void
+}
+
+declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1
+declare <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1>, <16 x i32>, <16 x i32>) #1
+declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
+declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
+declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }