[llvm] r269312 - [Hexagon] Properly handle instruction selection of vsplat intrinsics

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Thu May 12 12:21:40 2016
New Revision: 269312

URL: http://llvm.org/viewvc/llvm-project?rev=269312&view=rev
Log:
[Hexagon] Properly handle instruction selection of vsplat intrinsics

Added:
    llvm/trunk/test/CodeGen/Hexagon/vsplat-isel.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=269312&r1=269311&r2=269312&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Thu May 12 12:21:40 2016
@@ -1044,11 +1044,12 @@ SDNode *HexagonDAGToDAGISel::SelectIntri
     return SelectCode(N);
   }
 
-  SDValue const &V = N->getOperand(1);
+  SDValue V = N->getOperand(1);
   SDValue U;
   if (isValueExtension(V, Bits, U)) {
     SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
-      N->getOperand(0), U);
+                                N->getOperand(0), U);
+    ReplaceUses(N, R.getNode());
     return SelectCode(R.getNode());
   }
   return SelectCode(N);

Added: llvm/trunk/test/CodeGen/Hexagon/vsplat-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/vsplat-isel.ll?rev=269312&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/vsplat-isel.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/vsplat-isel.ll Thu May 12 12:21:40 2016
@@ -0,0 +1,10 @@
+; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
+; CHECK: vsplatb
+
+declare i32 @llvm.hexagon.S2.vsplatrb(i32) #0
+
+define i32 @foo(i8 %x) {
+  %p0 = zext i8 %x to i32
+  %p1 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %p0)
+  ret i32 %p1
+}