[llvm] r269209 - [X86][SSE] Avoid repeatedly calling MCInst::getNumOperands(). NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed May 11 10:36:32 PDT 2016
Author: rksimon
Date: Wed May 11 12:36:32 2016
New Revision: 269209
URL: http://llvm.org/viewvc/llvm-project?rev=269209&view=rev
Log:
[X86][SSE] Avoid repeatedly calling MCInst::getNumOperands(). NFCI.
Modified:
llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp
Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp?rev=269209&r1=269208&r2=269209&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp (original)
+++ llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp Wed May 11 12:36:32 2016
@@ -162,6 +162,7 @@ bool llvm::EmitAnyX86InstComments(const
// If this is a shuffle operation, the switch should fill in this state.
SmallVector<int, 8> ShuffleMask;
const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
+ unsigned NumOperands = MI->getNumOperands();
switch (MI->getOpcode()) {
default:
@@ -176,9 +177,9 @@ bool llvm::EmitAnyX86InstComments(const
case X86::BLENDPDrmi:
case X86::VBLENDPDrmi:
case X86::VBLENDPDYrmi:
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
+ if (MI->getOperand(NumOperands - 1).isImm())
DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f64, 0),
- MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
Src1Name = getRegName(MI->getOperand(1).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
@@ -192,9 +193,9 @@ bool llvm::EmitAnyX86InstComments(const
case X86::BLENDPSrmi:
case X86::VBLENDPSrmi:
case X86::VBLENDPSYrmi:
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
+ if (MI->getOperand(NumOperands - 1).isImm())
DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f32, 0),
- MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
Src1Name = getRegName(MI->getOperand(1).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
@@ -208,9 +209,9 @@ bool llvm::EmitAnyX86InstComments(const
case X86::PBLENDWrmi:
case X86::VPBLENDWrmi:
case X86::VPBLENDWYrmi:
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
+ if (MI->getOperand(NumOperands - 1).isImm())
DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i16, 0),
- MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
Src1Name = getRegName(MI->getOperand(1).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
@@ -222,9 +223,9 @@ bool llvm::EmitAnyX86InstComments(const
// FALL THROUGH.
case X86::VPBLENDDrmi:
case X86::VPBLENDDYrmi:
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
+ if (MI->getOperand(NumOperands - 1).isImm())
DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i32, 0),
- MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
Src1Name = getRegName(MI->getOperand(1).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
@@ -240,8 +241,8 @@ bool llvm::EmitAnyX86InstComments(const
case X86::VINSERTPSzrm:
DestName = getRegName(MI->getOperand(0).getReg());
Src1Name = getRegName(MI->getOperand(1).getReg());
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
- DecodeINSERTPSMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ if (MI->getOperand(NumOperands - 1).isImm())
+ DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
break;
@@ -296,7 +297,7 @@ bool llvm::EmitAnyX86InstComments(const
break;
CASE_MOVDUP(MOVSLDUP, r)
- Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
+ Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
// FALL THROUGH.
CASE_MOVDUP(MOVSLDUP, m)
DestName = getRegName(MI->getOperand(0).getReg());
@@ -304,7 +305,7 @@ bool llvm::EmitAnyX86InstComments(const
break;
CASE_MOVDUP(MOVSHDUP, r)
- Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
+ Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
// FALL THROUGH.
CASE_MOVDUP(MOVSHDUP, m)
DestName = getRegName(MI->getOperand(0).getReg());
@@ -312,7 +313,7 @@ bool llvm::EmitAnyX86InstComments(const
break;
CASE_MOVDUP(MOVDDUP, r)
- Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
+ Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
// FALL THROUGH.
CASE_MOVDUP(MOVDDUP, m)
DestName = getRegName(MI->getOperand(0).getReg());
@@ -324,9 +325,9 @@ bool llvm::EmitAnyX86InstComments(const
case X86::VPSLLDQYri:
Src1Name = getRegName(MI->getOperand(1).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
+ if (MI->getOperand(NumOperands - 1).isImm())
DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
- MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
break;
@@ -335,9 +336,9 @@ bool llvm::EmitAnyX86InstComments(const
case X86::VPSRLDQYri:
Src1Name = getRegName(MI->getOperand(1).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
+ if (MI->getOperand(NumOperands - 1).isImm())
DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
- MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
break;
@@ -351,9 +352,9 @@ bool llvm::EmitAnyX86InstComments(const
case X86::VPALIGNR256rm:
Src2Name = getRegName(MI->getOperand(1).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
+ if (MI->getOperand(NumOperands - 1).isImm())
DecodePALIGNRMask(getRegOperandVectorVT(MI, MVT::i8, 0),
- MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
break;
@@ -366,9 +367,9 @@ bool llvm::EmitAnyX86InstComments(const
case X86::VPSHUFDmi:
case X86::VPSHUFDYmi:
DestName = getRegName(MI->getOperand(0).getReg());
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
+ if (MI->getOperand(NumOperands - 1).isImm())
DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::i32, 0),
- MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
break;
@@ -381,9 +382,9 @@ bool llvm::EmitAnyX86InstComments(const
case X86::VPSHUFHWmi:
case X86::VPSHUFHWYmi:
DestName = getRegName(MI->getOperand(0).getReg());
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
+ if (MI->getOperand(NumOperands - 1).isImm())
DecodePSHUFHWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
- MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
break;
@@ -396,9 +397,9 @@ bool llvm::EmitAnyX86InstComments(const
case X86::VPSHUFLWmi:
case X86::VPSHUFLWYmi:
DestName = getRegName(MI->getOperand(0).getReg());
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
+ if (MI->getOperand(NumOperands - 1).isImm())
DecodePSHUFLWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
- MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
break;
@@ -407,9 +408,9 @@ bool llvm::EmitAnyX86InstComments(const
// FALL THROUGH.
case X86::MMX_PSHUFWmi:
DestName = getRegName(MI->getOperand(0).getReg());
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
+ if (MI->getOperand(NumOperands - 1).isImm())
DecodePSHUFMask(MVT::v4i16,
- MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
break;
@@ -509,9 +510,9 @@ bool llvm::EmitAnyX86InstComments(const
Src2Name = getRegName(MI->getOperand(2).getReg());
// FALL THROUGH.
CASE_SHUF(SHUFPD, m)
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
+ if (MI->getOperand(NumOperands - 1).isImm())
DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0),
- MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
Src1Name = getRegName(MI->getOperand(1).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
@@ -521,9 +522,9 @@ bool llvm::EmitAnyX86InstComments(const
Src2Name = getRegName(MI->getOperand(2).getReg());
// FALL THROUGH.
CASE_SHUF(SHUFPS, m)
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
+ if (MI->getOperand(NumOperands - 1).isImm())
DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0),
- MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
Src1Name = getRegName(MI->getOperand(1).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
@@ -535,18 +536,17 @@ bool llvm::EmitAnyX86InstComments(const
CASE_VSHUF(32X4, m) {
MVT VT;
bool HasMemOp;
- unsigned NumOp = MI->getNumOperands();
getVSHUF64x2FamilyInfo(MI, VT, HasMemOp);
- decodeVSHUF64x2FamilyMask(VT, MI->getOperand(NumOp - 1).getImm(),
+ decodeVSHUF64x2FamilyMask(VT, MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
DestName = getRegName(MI->getOperand(0).getReg());
if (HasMemOp) {
- assert((NumOp >= 8) && "Expected at least 8 operands!");
- Src1Name = getRegName(MI->getOperand(NumOp - 7).getReg());
+ assert((NumOperands >= 8) && "Expected at least 8 operands!");
+ Src1Name = getRegName(MI->getOperand(NumOperands - 7).getReg());
} else {
- assert((NumOp >= 4) && "Expected at least 4 operands!");
- Src2Name = getRegName(MI->getOperand(NumOp - 2).getReg());
- Src1Name = getRegName(MI->getOperand(NumOp - 3).getReg());
+ assert((NumOperands >= 4) && "Expected at least 4 operands!");
+ Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
+ Src1Name = getRegName(MI->getOperand(NumOperands - 3).getReg());
}
break;
}
@@ -591,9 +591,9 @@ bool llvm::EmitAnyX86InstComments(const
Src1Name = getRegName(MI->getOperand(1).getReg());
// FALL THROUGH.
CASE_VPERM(PERMILPS, m)
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
+ if (MI->getOperand(NumOperands - 1).isImm())
DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0),
- MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
DestName = getRegName(MI->getOperand(0).getReg());
break;
@@ -602,9 +602,9 @@ bool llvm::EmitAnyX86InstComments(const
Src1Name = getRegName(MI->getOperand(1).getReg());
// FALL THROUGH.
CASE_VPERM(PERMILPD, m)
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
+ if (MI->getOperand(NumOperands - 1).isImm())
DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0),
- MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
DestName = getRegName(MI->getOperand(0).getReg());
break;
@@ -616,9 +616,9 @@ bool llvm::EmitAnyX86InstComments(const
case X86::VPERM2F128rm:
case X86::VPERM2I128rm:
// For instruction comments purpose, assume the 256-bit vector is v4i64.
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
+ if (MI->getOperand(NumOperands - 1).isImm())
DecodeVPERM2X128Mask(MVT::v4i64,
- MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
Src1Name = getRegName(MI->getOperand(1).getReg());
DestName = getRegName(MI->getOperand(0).getReg());
@@ -630,8 +630,8 @@ bool llvm::EmitAnyX86InstComments(const
// FALL THROUGH.
case X86::VPERMQYmi:
case X86::VPERMPDYmi:
- if (MI->getOperand(MI->getNumOperands() - 1).isImm())
- DecodeVPERMMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
+ if (MI->getOperand(NumOperands - 1).isImm())
+ DecodeVPERMMask(MI->getOperand(NumOperands - 1).getImm(),
ShuffleMask);
DestName = getRegName(MI->getOperand(0).getReg());
break;
@@ -714,7 +714,7 @@ bool llvm::EmitAnyX86InstComments(const
CASE_PMOVZX(PMOVZXBW, r)
CASE_PMOVZX(PMOVZXBD, r)
CASE_PMOVZX(PMOVZXBQ, r)
- Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
+ Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
// FALL THROUGH.
CASE_PMOVZX(PMOVZXBW, m)
CASE_PMOVZX(PMOVZXBD, m)
@@ -725,7 +725,7 @@ bool llvm::EmitAnyX86InstComments(const
CASE_PMOVZX(PMOVZXWD, r)
CASE_PMOVZX(PMOVZXWQ, r)
- Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
+ Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
// FALL THROUGH.
CASE_PMOVZX(PMOVZXWD, m)
CASE_PMOVZX(PMOVZXWQ, m)
@@ -734,7 +734,7 @@ bool llvm::EmitAnyX86InstComments(const
break;
CASE_PMOVZX(PMOVZXDQ, r)
- Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
+ Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
// FALL THROUGH.
CASE_PMOVZX(PMOVZXDQ, m)
DecodeZeroExtendMask(MVT::i32, getZeroExtensionResultType(MI), ShuffleMask);
More information about the llvm-commits
mailing list