[PATCH] D19922: [AArch64] Fix DAG selection for cmps for fp16 type

[Weiming Zhao via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL269151: [AArch64] Fix DAG selection for cmps for fp16 type (authored by weimingz).

Changed prior to commit:
  http://reviews.llvm.org/D19922?vs=56845&id=56847#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D19922

Files:
  llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/trunk/test/CodeGen/AArch64/half.ll

Index: llvm/trunk/test/CodeGen/AArch64/half.ll
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/half.ll
+++ llvm/trunk/test/CodeGen/AArch64/half.ll
@@ -81,3 +81,15 @@
   store half %val16, half* %addr
   ret void
 }
+
+define i16 @test_fccmp(i1 %a) {
+;CHECK-LABEL: test_fccmp:
+;CHECK: fcmp
+  %cmp0 = fcmp ogt half 0xH3333, undef
+  %cmp1 = fcmp ogt half 0xH2222, undef
+  %x = select i1 %cmp0, i16 0, i16 undef
+  %or = or i1 %cmp1, %cmp0
+  %y = select i1 %or, i16 4, i16 undef
+  %r = add i16 %x, %y
+  ret i16 %r
+}
Index: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1229,6 +1229,7 @@
     if (VT == MVT::f16) {
       LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS);
       RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS);
+      VT = MVT::f32;
     }
     return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
   }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D19922.56847.patch
Type: text/x-patch
Size: 1088 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160511/cf7caf28/attachment.bin>