[PATCH] D11798: [mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions

[Simon Dardis via llvm-commits]

sdardis requested changes to this revision.
sdardis added a comment.
This revision now requires changes to proceed.

Can you add invalid tests for these instructions? More comments are inlined.


================
Comment at: lib/Target/Mips/Disassembler/MipsDisassembler.cpp:428
@@ +427,3 @@
+DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
+                      const void *Decoder);
+
----------------
Indentation, align "const void *Decoder" with "MCInst &MI" above.

================
Comment at: lib/Target/Mips/Disassembler/MipsDisassembler.cpp:438
@@ +437,3 @@
+DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
+                       const void *Decoder);
+
----------------
Here too.

================
Comment at: lib/Target/Mips/Disassembler/MipsDisassembler.cpp:608-609
@@ +607,4 @@
+static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
+                                          uint64_t Address,
+                                          const void *Decoder) {
+  InsnType Rt = fieldFromInstruction(insn, 21, 5);
----------------
Indentation.

================
Comment at: lib/Target/Mips/Disassembler/MipsDisassembler.cpp:678-679
@@ +677,4 @@
+static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
+                                           uint64_t Address,
+                                           const void *Decoder) {
+  InsnType Rt = fieldFromInstruction(insn, 21, 5);
----------------
Indentation.

================
Comment at: lib/Target/Mips/MicroMips32r6InstrFormats.td:87
@@ +86,3 @@
+
+class POP37_BOVC_FM_MMR6<string instr_asm> : MipsR6Inst, MMR6Arch<instr_asm> {
+  bits<5> rt;
----------------
Typo, BNVC not BOVC.

================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:193
@@ -183,1 +192,3 @@
+class BOVC_MMR6_ENC : POP35_BOVC_FM_MMR6<"bovc">;
+class BNVC_MMR6_ENC : POP37_BOVC_FM_MMR6<"bnvc">;
 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
----------------
Typo, Should  POP37_BNVC_FM_MMR6 for bnvc.

================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:1167
@@ +1166,3 @@
+  bit hasDelaySlot = 0;
+}
+
----------------
JARLC also defines RA.

================
Comment at: lib/Target/Mips/MicroMipsInstrInfo.td:851
@@ -851,1 +850,3 @@
+  def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>,
+              ISA_MICROMIPS32_NOT_MIPS32R6;
   def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
----------------
This needs to be marked as not 32R6/64R6.


http://reviews.llvm.org/D11798