[llvm] r268946 - [Hexagon] Treat all conditional branches as predicted (not-taken by default)
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Mon May 9 11:22:08 PDT 2016
Author: kparzysz
Date: Mon May 9 13:22:07 2016
New Revision: 268946
URL: http://llvm.org/viewvc/llvm-project?rev=268946&view=rev
Log:
[Hexagon] Treat all conditional branches as predicted (not-taken by default)
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
llvm/trunk/test/CodeGen/Hexagon/block-addr.ll
llvm/trunk/test/MC/Disassembler/Hexagon/jr.txt
llvm/trunk/test/MC/Hexagon/v60-misc.s
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td?rev=268946&r1=268945&r2=268946&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrAlias.td Mon May 9 13:22:07 2016
@@ -460,6 +460,38 @@ def : InstAlias<"$Pd=cmp.lt($Rs, $Rt)",
def : InstAlias<"$Pd=cmp.ltu($Rs, $Rt)",
(C2_cmpgtu PredRegs:$Pd, IntRegs:$Rt, IntRegs:$Rs), 0>;
+// maps if (!Pu) jumpr Rs -> if (!Pu) jumpr:nt Rs
+def : InstAlias<"if (!$Pu) jumpr $Rs",
+ (J2_jumprf PredRegs:$Pu, IntRegs:$Rs)>,
+ Requires<[HasV60T]>;
+
+// maps if (Pu) jumpr Rs -> if (Pu) jumpr:nt Rs
+def : InstAlias<"if ($Pu) jumpr $Rs",
+ (J2_jumprt PredRegs:$Pu, IntRegs:$Rs)>,
+ Requires<[HasV60T]>;
+
+// maps if (!Pu) jump $r15_2 -> if (!Pu) jump:nt $r15_2
+def : InstAlias<"if (!$Pu) jump $r15_2",
+ (J2_jumpf PredRegs:$Pu, brtarget:$r15_2)>,
+ Requires<[HasV60T]>;
+
+// maps if (Pu) jump $r15_2 -> if (Pu) jump:nt $r15_2
+def : InstAlias<"if ($Pu) jump $r15_2",
+ (J2_jumpt PredRegs:$Pu, brtarget:$r15_2)>,
+ Requires<[HasV60T]>;
+
+def : InstAlias<"if ($src) jump $r15_2",
+ (J2_jumpt PredRegs:$src, brtarget:$r15_2), 0>;
+
+def : InstAlias<"if (!$src) jump $r15_2",
+ (J2_jumpf PredRegs:$src, brtarget:$r15_2), 0>;
+
+def : InstAlias<"if ($src1) jumpr $src2",
+ (J2_jumprt PredRegs:$src1, IntRegs:$src2), 0>;
+
+def : InstAlias<"if (!$src1) jumpr $src2",
+ (J2_jumprf PredRegs:$src1, IntRegs:$src2), 0>;
+
// V6_vassignp: Vector assign mapping.
let hasNewValue = 1, opNewValue = 0, isAsmParserOnly = 1 in
def HEXAGON_V6_vassignpair: CVI_VA_DV_Resource <
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=268946&r1=268945&r2=268946&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Mon May 9 13:22:07 2016
@@ -1436,7 +1436,7 @@ class CondStr<string CReg, bit True, bit
string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
}
class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
- string S = Mnemonic # !if(Taken, ":t", !if(New, ":nt", ""));
+ string S = Mnemonic # !if(Taken, ":t", ":nt");
}
let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
@@ -1582,19 +1582,31 @@ let Defs = VolatileV3.Regs in {
let isTerminator = 1, hasSideEffects = 0 in {
defm J2_jump : JMP_base<"JMP", "">, PredNewRel;
- // Deal with explicit assembly
- // - never extened a jump #, always extend a jump ##
- let isAsmParserOnly = 1 in {
- defm J2_jump_ext : JMP_base<"JMP", "##">;
- defm J2_jump_noext : JMP_base<"JMP", "#">;
- }
-
defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel;
let isReturn = 1, isCodeGenOnly = 1 in
defm JMPret : JMPR_base<"JMPret">, PredNewRel;
}
+let validSubTargets = HasV60SubT in
+multiclass JMPpt_base<string BaseOp> {
+ let BaseOpcode = BaseOp in {
+ def tpt : T_JMP_c <0, 0, 1, "">; // Predicate true - taken
+ def fpt : T_JMP_c <1, 0, 1, "">; // Predicate false - taken
+ }
+}
+
+let validSubTargets = HasV60SubT in
+multiclass JMPRpt_base<string BaseOp> {
+ let BaseOpcode = BaseOp in {
+ def tpt : T_JMPr_c<0, 0, 1>; // predicate true - taken
+ def fpt : T_JMPr_c<1, 0, 1>; // predicate false - taken
+ }
+}
+
+defm J2_jumpr : JMPRpt_base<"JMPr">;
+defm J2_jump : JMPpt_base<"JMP">;
+
def: Pat<(br bb:$dst),
(J2_jump brtarget:$dst)>;
def: Pat<(retflag),
Modified: llvm/trunk/test/CodeGen/Hexagon/block-addr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/block-addr.ll?rev=268946&r1=268945&r2=268946&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/block-addr.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/block-addr.ll Mon May 9 13:22:07 2016
@@ -3,7 +3,7 @@
; Allow combine(..##JTI..):
; CHECK: r{{[0-9]+}}{{.*}} = {{.*}}#.LJTI
; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+<<#[0-9]+}})
-; CHECK: jumpr r{{[0-9]+}}
+; CHECK: jumpr:nt r{{[0-9]+}}
define void @main() #0 {
entry:
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/jr.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/jr.txt?rev=268946&r1=268945&r2=268946&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/jr.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/jr.txt Mon May 9 13:22:07 2016
@@ -17,7 +17,7 @@
0x00 0xc0 0x95 0x52
# CHECK: jumpr r21
0x00 0xc1 0x55 0x53
-# CHECK: if (p1) jumpr r21
+# CHECK: if (p1) jumpr:nt r21
0x03 0x40 0x45 0x85 0x00 0xcb 0x55 0x53
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) jumpr:nt r21
@@ -25,7 +25,7 @@
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) jumpr:t r21
0x00 0xc3 0x75 0x53
-# CHECK: if (!p3) jumpr r21
+# CHECK: if (!p3) jumpr:nt r21
0x03 0x40 0x45 0x85 0x00 0xcb 0x75 0x53
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) jumpr:nt r21
Modified: llvm/trunk/test/MC/Hexagon/v60-misc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/v60-misc.s?rev=268946&r1=268945&r2=268946&view=diff
==============================================================================
--- llvm/trunk/test/MC/Hexagon/v60-misc.s (original)
+++ llvm/trunk/test/MC/Hexagon/v60-misc.s Mon May 9 13:22:07 2016
@@ -1,5 +1,19 @@
# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -d - | FileCheck %s
+.L0:
+
+# CHECK: 5c00c000 { if (p0) jump:nt
+if (p0) jump .L0
+
+# CHECK: 5cffe1fe { if (!p1) jump:nt
+if (!p1) jump .L0
+
+# CHECK: 5340c200 { if (p2) jumpr:nt
+if (p2) jumpr r0
+
+# CHECK: 5361c300 { if (!p3) jumpr:nt
+if (!p3) jumpr r1
+
# CHECK: 1c2eceee { v14 = vxor(v14,{{ *}}v14) }
v14 = #0
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