[llvm] r268908 - [Sparc][LEON] Add UMAC and SMAC instruction support for Sparc LEON subtargets
Chris Dewhurst via llvm-commits
llvm-commits at lists.llvm.org
Mon May 9 04:55:16 PDT 2016
Author: lerochris
Date: Mon May 9 06:55:15 2016
New Revision: 268908
URL: http://llvm.org/viewvc/llvm-project?rev=268908&view=rev
Log:
[Sparc][LEON] Add UMAC and SMAC instruction support for Sparc LEON subtargets
This change adds SMAC (signed multiply-accumulate) and UMAC (unsigned multiply-accumulate) for LEON subtargets of the Sparc processor.
The new files LeonFeatures.td and leon-instructions.ll will both be expanded in future, so I want to leave them separate as small files for this review, to be expanded in future check-ins.
Note: The functions are provided only for inline-assembly provision. No DAG selection is provided.
Differential Revision: http://reviews.llvm.org/D19911
Added:
llvm/trunk/lib/Target/Sparc/LeonFeatures.td (with props)
llvm/trunk/test/MC/Sparc/leon-instructions.s (with props)
Modified:
llvm/trunk/lib/Target/Sparc/Sparc.td
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
llvm/trunk/lib/Target/Sparc/SparcSchedule.td
llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp
llvm/trunk/lib/Target/Sparc/SparcSubtarget.h
Added: llvm/trunk/lib/Target/Sparc/LeonFeatures.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/LeonFeatures.td?rev=268908&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Sparc/LeonFeatures.td (added)
+++ llvm/trunk/lib/Target/Sparc/LeonFeatures.td Mon May 9 06:55:15 2016
@@ -0,0 +1,24 @@
+//===-- LeonFeatures.td - Describe the Leon Features -------*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+
+//===----------------------------------------------------------------------===//
+// UMAC and SMAC support for LEON3 and LEON4 processors.
+//===----------------------------------------------------------------------===//
+
+//support to casa instruction; for leon3 subtarget only
+def UMACSMACSupport : SubtargetFeature<
+ "hasumacsmac",
+ "HasUmacSmac",
+ "true",
+ "Enable UMAC and SMAC for LEON3 and LEON4 processors"
+>;
Propchange: llvm/trunk/lib/Target/Sparc/LeonFeatures.td
------------------------------------------------------------------------------
svn:executable = *
Modified: llvm/trunk/lib/Target/Sparc/Sparc.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.td?rev=268908&r1=268907&r2=268908&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/Sparc.td (original)
+++ llvm/trunk/lib/Target/Sparc/Sparc.td Mon May 9 06:55:15 2016
@@ -46,6 +46,9 @@ def FeatureHardQuad
def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",
"Use the popc (population count) instruction">;
+//==== Features added predmoninantly for LEON subtarget support
+include "LeonFeatures.td"
+
//===----------------------------------------------------------------------===//
// Register File, Calling Conv, Instruction Descriptions
//===----------------------------------------------------------------------===//
@@ -111,26 +114,26 @@ def : Processor<"at697f", LEON2Itinerari
// LEON 3 FT generic
def : Processor<"leon3", LEON3Itineraries,
- [FeatureLeon]>;
+ [FeatureLeon, UMACSMACSupport]>;
// LEON 3 FT (UT699)
// TO DO: Place-holder: Processor specific features will be added *very* soon here.
def : Processor<"ut699", LEON3Itineraries,
- [FeatureLeon]>;
+ [FeatureLeon, UMACSMACSupport]>;
// LEON3 FT (GR712RC)
// TO DO: Place-holder: Processor specific features will be added *very* soon here.
def : Processor<"gr712rc", LEON3Itineraries,
- [FeatureLeon]>;
+ [FeatureLeon, UMACSMACSupport]>;
// LEON 4 FT generic
def : Processor<"leon4", LEON4Itineraries,
- [FeatureLeon]>;
+ [FeatureLeon, UMACSMACSupport]>;
// LEON 4 FT (GR740)
// TO DO: Place-holder: Processor specific features will be added *very* soon here.
def : Processor<"gr740", LEON4Itineraries,
- [FeatureLeon]> {}
+ [FeatureLeon, UMACSMACSupport]>;
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=268908&r1=268907&r2=268908&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Mon May 9 06:55:15 2016
@@ -49,6 +49,10 @@ def HasVIS3 : Predicate<"Subtarget->isVI
// point instructions.
def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
+// HasUMAC_SMAC - This is true when the target processor supports the
+// UMAC and SMAC instructions
+def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">;
+
// UseDeprecatedInsts - This predicate is true when the target processor is a
// V8, or when it is V9 but the V8 deprecated instructions are efficient enough
// to use when appropriate. In either of these cases, the instruction selector
@@ -1502,6 +1506,30 @@ let Predicates = [HasV9], Constraints =
[(set i32:$rd,
(atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
+// TODO: Add DAG sequence to lower these instructions. Currently, only provided
+// as inline assembler-supported instructions.
+let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in {
+ def SMACrr : F3_1<2, 0b111111,
+ (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
+ "smac $rs1, $rs2, $rd",
+ [], IIC_smac_umac>;
+
+ def SMACri : F3_2<2, 0b111111,
+ (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18),
+ "smac $rs1, $simm13, $rd",
+ [], IIC_smac_umac>;
+
+ def UMACrr : F3_1<2, 0b111110,
+ (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
+ "umac $rs1, $rs2, $rd",
+ [], IIC_smac_umac>;
+
+ def UMACri : F3_2<2, 0b111110,
+ (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18),
+ "umac $rs1, $simm13, $rd",
+ [], IIC_smac_umac>;
+}
+
let Defs = [ICC] in {
defm TADDCC : F3_12np<"taddcc", 0b100000>;
defm TSUBCC : F3_12np<"tsubcc", 0b100001>;
Modified: llvm/trunk/lib/Target/Sparc/SparcSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSchedule.td?rev=268908&r1=268907&r2=268908&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcSchedule.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcSchedule.td Mon May 9 06:55:15 2016
@@ -32,6 +32,7 @@ def IIC_fpu_sqrtd : InstrItinClass;
def IIC_fpu_abs : InstrItinClass;
def IIC_fpu_movs : InstrItinClass;
def IIC_fpu_negs : InstrItinClass;
+def IIC_smac_umac : InstrItinClass;
def IIC_fpu_stod : InstrItinClass;
def LEONIU : FuncUnit; // integer unit
@@ -79,6 +80,7 @@ def LEON3Itineraries : ProcessorItinerar
InstrItinData<IIC_iu_smul, [InstrStage<1, [LEONIU]>], [1, 1]>,
InstrItinData<IIC_iu_umul, [InstrStage<1, [LEONIU]>], [4, 1]>,
InstrItinData<IIC_iu_div, [InstrStage<1, [LEONIU]>], [35, 1]>,
+ InstrItinData<IIC_smac_umac, [InstrStage<1, [LEONIU]>], [2, 1]>,
InstrItinData<IIC_ticc, [InstrStage<1, [LEONIU, LEONFPU]>], [5, 1]>,
InstrItinData<IIC_ldstub, [InstrStage<1, [LEONIU, LEONFPU]>], [3, 1]>,
InstrItinData<IIC_fpu_muls, [InstrStage<1, [LEONFPU]>], [4, 1]>,
@@ -106,6 +108,7 @@ def LEON4Itineraries : ProcessorItinerar
InstrItinData<IIC_iu_smul, [InstrStage<1, [LEONIU]>], [1, 1]>,
InstrItinData<IIC_iu_umul, [InstrStage<1, [LEONIU]>], [4, 1]>,
InstrItinData<IIC_iu_div, [InstrStage<1, [LEONIU]>], [35, 1]>,
+ InstrItinData<IIC_smac_umac, [InstrStage<1, [LEONIU]>], [2, 1]>,
InstrItinData<IIC_ticc, [InstrStage<1, [LEONIU, LEONFPU]>], [5, 1]>,
InstrItinData<IIC_ldstub, [InstrStage<1, [LEONIU, LEONFPU]>], [3, 1]>,
InstrItinData<IIC_fpu_muls, [InstrStage<1, [LEONFPU]>], [4, 1]>,
Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=268908&r1=268907&r2=268908&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp Mon May 9 06:55:15 2016
@@ -29,10 +29,12 @@ void SparcSubtarget::anchor() { }
SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
StringRef FS) {
IsV9 = false;
+ IsLeon = false;
V8DeprecatedInsts = false;
IsVIS = false;
HasHardQuad = false;
UsePopc = false;
+ HasUmacSmac = false;
// Determine default and user specified characteristics
std::string CPUName = CPU;
Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.h?rev=268908&r1=268907&r2=268908&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcSubtarget.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.h Mon May 9 06:55:15 2016
@@ -34,6 +34,7 @@ class SparcSubtarget : public SparcGenSu
virtual void anchor();
bool IsV9;
bool IsLeon;
+ bool HasUmacSmac;
bool V8DeprecatedInsts;
bool IsVIS, IsVIS2, IsVIS3;
bool Is64Bit;
@@ -66,6 +67,7 @@ public:
bool isV9() const { return IsV9; }
bool isLeon() const { return IsLeon; }
+ bool hasUmacSmac() const { return HasUmacSmac; }
bool isVIS() const { return IsVIS; }
bool isVIS2() const { return IsVIS2; }
bool isVIS3() const { return IsVIS3; }
Added: llvm/trunk/test/MC/Sparc/leon-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Sparc/leon-instructions.s?rev=268908&view=auto
==============================================================================
--- llvm/trunk/test/MC/Sparc/leon-instructions.s (added)
+++ llvm/trunk/test/MC/Sparc/leon-instructions.s Mon May 9 06:55:15 2016
@@ -0,0 +1,12 @@
+! RUN: llvm-mc %s -arch=sparc -mcpu=leon3 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -arch=sparc -mcpu=ut699 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -arch=sparc -mcpu=gr712rc -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -arch=sparc -mcpu=leon4 -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -arch=sparc -mcpu=gr740 -show-encoding | FileCheck %s
+
+
+ ! CHECK: umac %i0, %l6, %o2 ! encoding: [0x95,0xf6,0x00,0x16]
+ umac %i0, %l6, %o2
+
+ ! CHECK: smac %i0, %l6, %o2 ! encoding: [0x95,0xfe,0x00,0x16]
+ smac %i0, %l6, %o2
Propchange: llvm/trunk/test/MC/Sparc/leon-instructions.s
------------------------------------------------------------------------------
svn:executable = *
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