[PATCH] D19894: AMDGPU: Fix not counting shader input registers

[Matt Arsenault via llvm-commits]

arsenm added a comment.

I found a problem with the generated input registers. If you have a case like
(<3 x i32> inreg, i64 inreg, i32 inreg), it correctly selects s0, s1, s2 for the vector, s[4:5] for the i64, and the final i32 picks the s3 in the alignment gap between the vector and i64. I'm guessing that changing the order this way will break something


http://reviews.llvm.org/D19894