[llvm] r268771 - [X86] Get rid of X32_NOREX_ADDR_ACCESS register class.
Quentin Colombet via llvm-commits
llvm-commits at lists.llvm.org
Fri May 6 11:22:49 PDT 2016
Author: qcolombet
Date: Fri May 6 13:22:48 2016
New Revision: 268771
URL: http://llvm.org/viewvc/llvm-project?rev=268771&view=rev
Log:
[X86] Get rid of X32_NOREX_ADDR_ACCESS register class.
According to H.J. Lu <hjl.tools at gmail.com>, this register class is never
used.
Modified:
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.td
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=268771&r1=268770&r2=268771&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Fri May 6 13:22:48 2016
@@ -174,8 +174,7 @@ X86RegisterInfo::getPointerRegClass(cons
case 2: // NOREX GPRs.
if (Subtarget.isTarget64BitLP64())
return &X86::GR64_NOREXRegClass;
- return Is64Bit ? &X86::X32_NOREX_ADDR_ACCESSRegClass
- : &X86::GR32_NOREXRegClass;
+ return &X86::GR32_NOREXRegClass;
case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
if (Subtarget.isTarget64BitLP64())
return &X86::GR64_NOREX_NOSPRegClass;
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=268771&r1=268770&r2=268771&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Fri May 6 13:22:48 2016
@@ -423,8 +423,6 @@ def GR64_NOREX_NOSP : RegisterClass<"X86
// FIXME: We could allow all 64bit registers, but we would need
// something to check that the 32 high bits are not set.
def X32_ADDR_ACCESS : RegisterClass<"X86", [i32], 64, (add GR32, RIP)>;
-def X32_NOREX_ADDR_ACCESS : RegisterClass<"X86", [i32], 64,
- (add GR32_NOREX, RIP)>;
// A class to support the 'A' assembler constraint: EAX then EDX.
def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
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