[PATCH] D16182: [mips][microMIPS][DSP] Implement BALIGN, BITREV, BPOSGE32, CMP*, CMPGDU*, CMPGU* and CMPU* instructions

[Simon Dardis via llvm-commits]

sdardis added a comment.

Test that bposge32 is invalid for microMIPS32r6 and microMIPS64r6 invalid.s tests along with a comment noting that it is a DSP instruction.


================
Comment at: lib/Target/Mips/MicroMipsDSPInstrFormats.td:279
@@ +278,3 @@
+
+class POOL32_3RB0_FMT<string opstr, bits<6> pool, bits<10> op>
+    : MMDSPInst<opstr> {
----------------
"pool" does not need to be a parameter for this class. Bits 31-26 should correspond to POOL32A's opcode. And it should be named "POOL32A_3RB0_FMT". Sorry for the bikeshedding there.

================
Comment at: lib/Target/Mips/MicroMipsDSPInstrFormats.td:303
@@ +302,2 @@
+  let Inst{9-0}   = op;
+}
----------------
Add a class describing POOL32S 3 register bit0 format for cmpgu.<cond>.qb.

================
Comment at: lib/Target/Mips/MicroMipsDSPInstrInfo.td:167-172
@@ +166,8 @@
+class CMPGDU_LE_QB_MMR2_ENC : POOL32_3RB0_FMT<"cmpgdu.le.qb", 0, 0b1000000101>;
+class CMPGU_EQ_QB_MM_ENC
+    : POOL32_3RB0_FMT<"cmpgu.eq.qb", 0b010110, 0b0011000101>;
+class CMPGU_LT_QB_MM_ENC
+    : POOL32_3RB0_FMT<"cmpgu.lt.qb", 0b010110, 0b0100000101>;
+class CMPGU_LE_QB_MM_ENC
+    : POOL32_3RB0_FMT<"cmpgu.le.qb", 0b010110, 0b0101000101>;
+class CMPU_EQ_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.eq.qb", 0b1001000101>;
----------------
These should inherit from POOL32S_3RB0_FMT.

================
Comment at: test/MC/Disassembler/Mips/micromips32r3/valid-dsp.txt:3
@@ +2,2 @@
+
+0x43 0x60 0x00 0xab # CHECK: bposge32 342
----------------
This should go in the micromips-dsp and micromips-dspr2 sets of tests.

================
Comment at: test/MC/Mips/micromips/valid-dsp.s:4
@@ +3,2 @@
+  .set noat
+  bposge32 342                 # CHECK: bposge32 342            # encoding: [0x43,0x60,0x00,0xab]
----------------
This should go in the relevant existing micromips-dsp/micromips-dspr2 tests.


http://reviews.llvm.org/D16182